 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a tmel sam4sp32a cortex- m4 prime soc prelim in ary datasheet features ? core ? arm ? cortex ?- m4 with a 2kbytes cache running at 120mhz ? memory protection unit (mpu) ? dsp instruction set ? thumb ?- 2 instruction set ? memories ? 2048 kbytes embedded flash with optional dual bank and cache memory ? 160 kbytes embedded sram ? 16 kbytes rom with embedded boot loader routines (uart, usb) and iap routines ? system ? embedded voltage regulator f or single supply operation ? power - on- reset (por), brown - out detector (bod) and watchdog for safe operation ? quartz or ceramic resonator oscillators: 3 to 20 mhz main power with failure detection and optional low - power 32.768 khz for rtc or device clock ? rtc with gregorian and persian calendar mode, waveform generation in low power modes ? rtc clock calibration circuitry for 32.768 khz crystal frequency compensation ? high precision 8/12 mhz factory trimmed internal rc oscillator with 4 mhz default frequency for device startup. in - application trimming access for frequency adjustment ? slow clock internal rc oscillator as permanent low - power mode device clock ? two plls up to 240 mhz for device clock and for usb ? temperature sensor ? up to 22 peripheral dma (pdc) channels ? low power modes ? sleep and backup modes, down to 1 a in backup mode ? ultra low - power rtc ? peripherals ? usb 2.0 device: 12 mbps, 2668 byte fifo, up to 8 bidirectional endpoints. on - chip transceiver ? 2 usarts with iso7816, irda ?, rs - 485, manchester and modem mode ? two 2 - wire uarts ? 2 two wire interface (i2c compatible), 1 synchronous serial controller (ssc) ? 2 three - channel 16 - bit timer/counter with capture, waveform, compare and pwm mode. quadrature decoder logic and 2 - bit gray up/down counter for stepper motor ? 4 - channel 16 - bit pwm with complementary output, fault input, 12 - bit dead time generator counter 43020a - atpl - 09/12 www.datasheet.net/ datasheet pdf - http://www..co.kr/
a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 2 ? 32- bit real - time timer and rtc with calendar and alarm features ? one analog comparator with flexible input selection ? 32- bit cyclic redundancy check calculation u nit (crccu) ? write protected registers ? i/o ? up to 38 i/o lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on - die series resistor termination ? three 32 - bit parallel input/output controllers, peripheral dma assisted parallel capture mode ? prime plc modem ? power line carrier modem for 50 and 60 hz mains ? 97- carrier ofdm prime compliant ? baud rate selectable: 21400 to 128600 bps ? differential bpsk, qpsk, 8 - psk modulations ? automatic gain control and signal amplitude tracking ? embedded on - chip dmas ? media access control ? viterbi decoding and crc prime compliant ? 128- bit aes encryption ? channel sensing and collision pre - detection ? package ? 128- lead lqfp ? pb - free and rohs compliant ? typical applications ? prime smart meters ? prime d ata concentrator www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 3 description the sam4sp32a is a new evolution of sam4sd32 flash microcontroller based on the high performance 32 - bit arm cortex - m4 risc processor with a prime power line communication modem soc integrated. the sam4sp32a operates at a maximum speed of 120 mhz and features with a 2048 kbytes of flash, with optional dual bank implementation a nd 2kbytes of cache memory, 160 kbytes of sram, and 32kbytes embedded sram memory available for prime specification requirements. the peripheral set mainly includes a certified prime power line communication transceiver with a featured class d power amplifier and a set of hardware accelerators blocks to execute the heavy tasks of the prime protocol without the interruption of the cortex - m4 cpu. furthermore, the sam4sp32a includes a full speed usb device port with embedded transceiver, , 2x usarts, 2x uarts, 2x twis, an i2s, as well as 1 pwm timer, 2x three channel general - purpose 16 - bit timers (with stepper motor and quadrature decoder l ogic support), an rtc, a synchronous serial controller (ssc) and an analog comparator. the atmel sam4sp32a soc device combines robust and high performances prime plc modem with a powerfull cortex - m4 microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set. this enables the sam4sp32a to sustain a wide range of applications including prime smart g ri d an d data concentrator solutions . sam4sp32a operates from 3.0v to 3.6 v www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 4 table of contents 1. block diagram ................................ ................................ .................... 8 2. package and pinout ................................ ........................................... 9 2.1 128- lead lqfp package outline ................................ ................................ .. 9 2.2 128 - lead lqfp pinout ................................ ................................ ............... 10 3. signal description ................................ ................................ ............ 11 4. pin description ................................ ................................ ................. 15 5. power consi derations ................................ ...................................... 26 5.1 power supplies ................................ ................................ .......................... 26 5.2 voltage regulator ................................ ................................ ....................... 26 5.3 typical powering schematics ................................ ................................ ...... 26 5.4 active mode ................................ ................................ ............................... 29 5.5 low - power modes ................................ ................................ ...................... 29 5.5.1 backup mode ................................ ................................ ................ 29 5.5.2 wait mode ................................ ................................ .................... 29 5.5.3 sleep mode ................................ ................................ .................. 30 5.5.4 low power mode summary table ................................ ................. 30 5.6 wake - up sources ................................ ................................ ....................... 32 5.7 fast startup ................................ ................................ ................................ 33 6. input/output lines ................................ ................................ ............ 34 6.1 general purpose i/o lines ................................ ................................ .......... 34 6.2 syst em i/o lines ................................ ................................ ........................ 34 6.2.2 serial wire jtag debug port (swj - dp) pins ................................ 35 6.3 test pin ................................ ................................ ................................ ...... 35 6.4 nrst pin ................................ ................................ ................................ ... 36 6.5 erase pin ................................ ................................ ................................ . 36 7. processor and architecture .............................................................. 37 7.1 arm cortex - m4 processor ................................ ................................ ......... 37 7.2 apb/ahb bridge ................................ ................................ ......................... 37 7.3 matrix master ................................ ................................ .............................. 37 7.4 matrix slaves ................................ ................................ .............................. 37 7.5 master to slave access ................................ ................................ ............... 38 7.6 peripherical dma controller ................................ ................................ ........ 38 7.7 debug and test features ................................ ................................ ............ 39 8. sam4sp32a product mapping ................................ ........................ 40 9. memories ................................ ................................ ......................... 41 9.1 embedded memories ................................ ................................ .................. 41 9.1.1 internal sram ................................ ................................ .............. 41 9.1.2 intern al rom ................................ ................................ ................ 41 9.1.3 embedded flash ................................ ................................ ........... 41 9.1.3.1 flash overview ................................ ............................ 41 9.1.3.2 enhanced embedded flash controller .......................... 43 9.1.3.3 flash speed ................................ ................................ 43 9.1.3.4 lock regions ................................ ............................... 44 9.1.3.5 security bit feature ................................ ...................... 44 9.1.3.6 calibration bits ................................ ............................. 44 9.1.3.7 unique identifier ................................ ........................... 44 9.1.3.8 user signature ................................ ............................. 44 9.1.3.9 fa st flash programming interface ................................ 44 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 5 9.1.3.10 sam - ba boot ................................ ............................... 45 9.1.3.11 gpnvm bits ................................ ................................ 45 9.1.4 boot strategies ................................ ................................ ............. 45 10. system controller ................................ ................................ ............ 46 10.1 system controller and peripherals mapping ................................ ................ 47 10.2 power - on- reset, brownout and supply monitor ................................ ........... 47 10.2.1 power - on - reset ................................ ................................ ........... 47 10.2.2 brownout detector on vddcore ................................ .................. 47 10.2.3 supply monitor on vddio ................................ ............................. 47 10.3 reset controller ................................ ................................ .......................... 47 10.4 supply controller (supc) ................................ ................................ ........... 47 10.5 clock generator ................................ ................................ ......................... 48 10.6 power management controller ................................ ................................ .... 49 10.7 watchdog timer ................................ ................................ ......................... 50 10.8 systick timer ................................ ................................ ............................. 50 10.9 real time timer ................................ ................................ ......................... 50 10.10 real time clock ................................ ................................ ......................... 50 10.11 general - purpose backup registers ................................ ............................. 50 10.12 nested vectored interrupt controller ................................ ........................... 50 10.13 chip identification ................................ ................................ ....................... 51 10.14 uart ................................ ................................ ................................ ........ 51 10.15 pio controllers ................................ ................................ ........................... 51 10.16 peripheral identifiers ................................ ................................ ................... 53 10.17 peripheral signal multiplexing on i/o lines ................................ .................. 54 10.17.1 pio controller a multiplexing ................................ ......................... 54 10.17.2 pio controller b multiplexing ................................ ......................... 55 10.17.3 pio controller c multiplexing ................................ ......................... 55 11. embedded peripherals overview ..................................................... 56 11.1 two wire interface (twi) ................................ ................................ ............ 56 11.2 universal asynchronous receiver transceiver (uart) ................................ 56 11.3 usart ................................ ................................ ................................ ....... 56 11.4 synchronous serial controller (ssc) ................................ ........................... 57 11.5 timer counter (tc) ................................ ................................ ..................... 57 11.6 pulse width modulation controller (pwm) ................................ ................... 57 11.7 usb device port (udp) ................................ ................................ .............. 58 11.8 analog comparator ................................ ................................ ..................... 58 11.9 cyclic redundancy check calculation unit (crccu) ................................ .. 59 11.10 plc brigde ................................ ................................ ................................ . 59 12. prime plc transceiver ................................ ................................ .. 60 12.1 sam4sp32a prime phy layer ................................ ................................ . 61 12.1.1 sam4sp32a phy layer ................................ ............................... 61 12.1.1 .2 transmission and reception branches ......................... 62 12.1.1.3 carrier detection ................................ .......................... 62 12.1.1.4 analog front end control ................................ .............. 63 12.1.1.5 power supply sensing: vsense and psense ............ 63 12.1.1.6 gain control ................................ ................................ 64 12.1.1.7 line impedance control ................................ ............... 64 12.1.1.8 txrx control ................................ ................................ 65 12.1.2 phy parameters ................................ ................................ ........... 65 12.1.3 phy protocal data unit (ppdu) format ................................ ......... 66 12.1.4 phy service specification ................................ ............................. 66 12.1.5 phy layer registers ................................ ................................ ...... 68 12.1.5.1 phy_sfr register ................................ ...................... 68 12.1.5.2 sys_config register ................................ ................ 69 12.1.5.3 phy_config register ................................ ................ 70 12.1.5.4 attenuation register ................................ .............. 71 12.1.5.5 att_chirp register ................................ ................... 72 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 6 12.1.5.6 att _signal register ................................ ................. 73 12.1.5.7 tx_time registers ................................ ...................... 74 12.1.5.8 timer_frame registers ................................ ............ 75 12.1.5.9 timer_beacon_ref registers ................................ . 76 12.1.5.10 rx_level registers ................................ ................... 77 12.1.5.11 rssi_min register ................................ ...................... 78 12.1.5.12 rssi_avg register ................................ ..................... 79 12.1.5.13 rssi_max register ................................ ..................... 80 12.1.5.14 cinr_min register ................................ ..................... 81 12.1.5.15 cinr_avg register ................................ .................... 82 12.1.5.16 cinr_max register ................................ .................... 83 12.1.5.17 evm_header registers ................................ ............. 84 12.1.5.18 evm_payload registers ................................ ........... 85 12.1.5.19 evm_header_acum registers ................................ . 86 12.1.5.20 evm_payload_acum registers ............................... 87 12.1.5.21 rms_calc register ................................ ................... 88 12.1.5.22 vsense_config register ................................ ......... 89 12.1.5.23 num_fails register ................................ ................... 90 12.1.5.24 ttrans register ................................ ........................ 91 12.1.5 .25 agc0_krssi register ................................ ................ 92 12.1.5.26 agc1 krssi register ................................ ................. 93 12.1.5.27 zero_cross_time registers ................................ ... 94 12.1.5.28 zero_cross_config register ............................... 95 12.1.5.29 psensecycles registers ................................ ......... 96 12.1.5.30 mean registers ................................ .......................... 97 12.1.5.31 pmax registers ................................ ........................... 98 12.1.5.32 trans_psense register ................................ ........... 99 12.1.5.33 p_th registers ................................ ......................... 100 12.1.5.34 maxpot registers ................................ .................... 101 12.1.5.35 numcycles register ................................ ............... 102 12.1.5.36 a_nummilis register ................................ ............... 103 12.1.5.37 emit_config register ................................ ............. 104 12.1.5.38 afe_ctl register ................................ ..................... 105 12.1.5.39 r registers ................................ ................................ 106 12.1.5.40 phy_errors registers ................................ ........... 107 12.1.5.41 fft_mode registers ................................ ................ 108 12.1.5.42 agc_config register ................................ ............. 109 12.1.5.43 sat_th registers ................................ ..................... 111 12.1.5.44 agc1_th registers ................................ .................. 112 12.1 .5.45 agc0_th registers ................................ .................. 113 12.1.5.46 agc_pads register ................................ ................. 114 12.2 sam4sp32a mac layer ................................ ................................ .......... 115 12.2.1 cyclic redundancy check (crc) ................................ ................ 115 12.2.2 advanced encryption standard (aes) ................................ .......... 117 12.2.3 mac layer registers ................................ ................................ .. 118 12.2.3.1 sna registers ................................ ........................... 118 12.2.3.2 viterbi_ber_hard register ................................ .. 119 12.2.3.3 viterbi_ber_soft register ................................ ... 120 12.2.3.4 err_crc32_mac registers ................................ .... 121 12.2.3.5 err_crc8_mac registers ................................ ...... 122 12.2.3.6 err_crc8_aes registers ................................ ....... 123 12.2.3.7 err_crc8_mac_hd registers ................................ 124 12.2.3.8 err_crc8_phy registers ................................ ....... 125 12.2.3.9 false_det_config register ................................ . 126 12.2.3.10 false_det registers ................................ ............... 127 12.2.3.11 max_len_dbpsk register ................................ ....... 128 12.2.3.12 max_len_dbpsk_vtb register .............................. 129 12.2.3.13 max_len_dqpsk register ................................ ...... 130 12.2.3.14 max_len_dqpsk_vtb registers ............................ 131 12.2.3.15 max_len_d8psk registers ................................ ..... 132 12.2.3.16 max_len_d8psk_vtb regi ster .............................. 133 12.2.3.17 aes_pad_len register ................................ ............ 134 12.2.3.18 aes_data_in registers ................................ ........... 135 12.2.3.19 aes_data_out registers ................................ ....... 136 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 7 12.2.3.20 key_periph registers ................................ ............. 137 12.2.3.21 key_phy registers ................................ .................. 138 12.2.3.22 aes_sfr register ................................ .................... 139 13. electrical characteristics ................................ ................................ 140 13.1 absolute maximum ratings ................................ ................................ ....... 140 13.2 dc characteristics ................................ ................................ .................... 141 13.3 power consumption ................................ ................................ ................. 148 13.3.1 backup mode current consuption ................................ ............... 148 13.3.1.1 configuration a ................................ .......................... 148 13.3.1 .2 configuration b ................................ .......................... 148 13.3.2 sleep and wait mode current consumption ................................ . 149 13.3.2.1 sleep mode ................................ ............................... 149 13.3.2.2 wait mode ................................ ................................ . 151 13.3.3 active mode power consumption ................................ ................ 152 13.3.4 peripheral power consumption in active mode ............................ 154 13.4 oscillator characteristics ................................ ................................ .......... 156 13.4.1 32 khz rc oscillator characteristics ................................ ........... 156 13.4.2 4/8/12 mhz rc oscillators characteristics ................................ ... 157 13.4.3 32.768 khz crystal oscillator characteristics ............................... 158 13.4.4 32.768 khz crystal characteristics ................................ .............. 159 13.4.5 3 to 20 mhz crystal oscillator characteristics .............................. 159 13.4.6 3 to 20 mhz crystal characteristics ................................ ............. 160 13.4.7 crystal oscillator design considerations information .................... 161 13.4.7.1 choosing a crystal ................................ ..................... 161 13.4 .7.2 printed circuit board (pcb) ................................ ........ 161 13.5 plla, pllb characteristics ................................ ................................ ...... 162 13.6 usb transceiver characteristics ................................ ............................... 163 13.6.1 typical connections ................................ ................................ .... 163 13.6.2 electrical characteristics ................................ ............................. 163 13.6.3 switching characteristics ................................ ............................ 164 13.7 analog comparator characteristics ................................ ........................... 165 13.8 temperature sensor ................................ ................................ ................. 166 13.9 ac characteristics ................................ ................................ .................... 167 13.9.1 master clock characteristics ................................ ....................... 167 13.9.2 i/o characteristics ................................ ................................ ....... 167 13.9.3 ssc timings ................................ ................................ ............... 169 13.9.3.2 ssc timings ................................ .............................. 173 13.9.4 smc timings ................................ ................................ .............. 175 13.9.4.1 read timings ................................ ............................. 175 13.9.4.2 write timings ................................ ............................. 177 13.9.5 usart in spi mode timings ................................ ....................... 180 13.9.5.2 usart spi timings ................................ .................. 182 13.9.6 two - wire serial interface characteristics ................................ ..... 184 13.9.7 embedded flash characteristics ................................ ................. 186 13.10 recommended operating conditions ................................ ........................ 189 14. mechanical c haracteristics ............................................................ 190 15. ordering information ................................ ...................................... 191 16. revision history ................................ ............................................. 192 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 8 1. block diagram figure 1 - 1. sam4sp32a block diagram peripheral bridge flash 2*1024 kbytes sram 160 kbytes rom 16 kbytes cmcc(2 kb cache) flash unique identifier voltage regulator 4-layer ahb bus matrix fmax 120 mhz jtag & serial wire cortex m-4 processor fmax 120mhz dsp 24-bit systick counter n v i c mpu in-circuit emulator pdc pdc pdc pdc pdc pdc pdc pwm timer counter a usart1 usart0 uart1 uart0 twi1 twi0 tc[0..2] pioa / piob wdt sm rstc rtc por rtt 8 gpbreg rc 32 khz osc 32 khz supc 3-20 mhz osc pmc rc osc 12/8/4 mhz pllb plla system controller pdc pdc pdc pio plc_bridge analog comparator crc unit prime plc transceiver transceiver usb 2.0 full speed 2668 bytes fifo ssc 32 kbytes sram pwmh[0:3] pwml[0:3] pwmfi0 rxd1 txd1 sck1 rts1 cts1 tclk[0] tioa[0:1] tiob[0:1] rts0 cts0 txd0 sck0 twd1 urxd0 utxd0 urxd1 utxd1 rxd0 twck0 twd0 twck1 adc ch. rk advref intest1 intest2 intest3 intest4 intest5 intest6 tf tk piodc[1:0] piodcen1 piodcen2 piodcclk dpp dmm vddio vddcore vddpll rtcout0 rtcout1 nrst xin xout xin32 xout32 erase tst pck0- pck2 tdi jtagsel tck/swclk tms/swdio td0 vddin vddout12 agc rsta dbg4 dbg3 dbg2 dbgi vnr afe_himp emit[1:6] gnd vddout18 vddin vddcore vddio plc_clockout plc_clockin avrl avrh avdd agnd intest12 intest11 intest10 intest9 intest8 intest7 ainplc rsts gpio gpio www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 9 2. package and pinout 2.1 128- lead lqfp package outline figure 2 - 1. orientation of the 128 - lead package 1 32 33 64 65 96 97 128 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 10 2.2 128- lead lqfp pinout table 2 - 1. sam4sp32a 128 - lead lqfp pinout 1 advref 33 pc0 65 intest7 97 tdo/traceswo/ pb5 2 gnd 34 gnd 66 intest10 98 dbg0 3 gnd 35 vddio 67 intest12 99 jtagsel 4 agc 36 pa16/pgmd4 68 intest11 100 dbg1 5 gnd 37 nc 69 tdi/pb4 101 dbg2 6 vddio 38 pa15/pgmd3 70 vddio 102 gnd 7 agnd 39 intest1 71 pa6/pgmnoe 103 vddio 8 pb0 40 intest2 72 pa5/pgmrdy 104 dbg3 9 avdd 41 pa24/pgmd12 73 pa4/pgmncmd 105 tms/swdio/pb6 10 pb1 42 pc5 74 gnd 106 dbg4 11 agnd 43 nc 75 emit1 107 rsta 12 avdd 44 nc 76 vddio 108 rsts 13 vrh 45 vddcore 77 nrst 109 tck/swclk/pb7 14 pb2 46 gnd 78 tst 110 gnd 15 ainplc 47 pa25/pgmd13 79 emit2 111 vddout18 16 pb3 48 vddout18 80 emit3 112 gnd 17 vrl 49 nc 81 pa3 113 vddcore 18 vddin 50 intest3 82 emit4 114 vddin 19 vddout12 51 intest4 83 pa2/pgmen2 115 erase/pb12 20 pa17/pgmd5 52 intest5 84 gnd 116 vddin 21 pc26 53 pa10/pgmm2 85 vddio 117 ddm/pb10 22 pa18/pgmd6 5 4 gnd 86 emit5 118 ddp/pb11 23 pa21/pgmd9 55 pa9/pgmm1 87 vddio 119 vddio 24 vddcore 56 intest6 88 vddio 120 vddio 25 pa19/pgmd7 57 gnd 89 nc 121 plc_clocki n 26 pa22/pgmd10 58 vddio 90 emit6 122 pb13/dac0 27 pa23/pgmd11 59 pa8/xout32/ pgmm0 91 gnd 123 plc_clock out 28 pa20/pgmd8 60 intest9 92 vddio 124 gnd 29 gnd 61 gnd 93 afe_himp 125 pb8/xout 30 vddio 62 pa7/xin32/ pgmnvalid 94 pa1/pgmen1 126 gnd 31 nc 63 intest8 95 pa0/pgmen0 127 pb9/pgmck/xin 32 nc 64 vddio 96 vnr 128 vddpll www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 11 3. signal description table 3 - 1. signal description list signal name function type active level voltage reference comm e n ts power supplies vddio peripherals i/o lines and usb transceiver power supply power 3v to 3v vdd in voltage regulator input, adc, dac and analog comparator power supply power 3v to 3v vdd core power the core, the embedded memories and the peripherals power 1v to 132v vddpll oscillator and pll power supply power 1v to 132v vddout1 ldo output power supply power 1v ouput vddout12 voltage regulator output power 12v output avdd analog converter power supply power 3v to 3v agnd analog ground ground gnd digital ground ground clocks, oscillators and plls xin main oscillator input input vddio reset state - pio input - internal pull - up disabled - schmitt trigger enabled (1) xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output pck - pck2 programmable clock output output reset state - pio input - internal pull - up enabled - schmitt trigger enabled (1) plc_clockin external clock input reference input plc_clockout external clock output reference output analog input voltage reference ainplc direct - analog input voltage analog avrh analog input high voltage reference analog avrl analog input low voltage reference analog adverf analog comparator reference analog www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 12 table 3 - 1. signal description list (continued) signal name function type active level voltage reference comm e n ts real time clock rtcout programmable rtc waveform output output vddio reset state - pio input - internal pull - up disabled - schmitt trigger enabled (1) rtcout1 programmable rtc waveform output output serial wire/jtag debug port - swj - dp tck/swclk test clock/serial wire clock input vddio reset state - swj - dp mode - internal pull - up disabled - schmitt trigger enabled (1) tdi test data in input tdo/traceswo test data out / trace asynchronous data out output tms/swdio test mode select /serial wire input/output input/ i/o jtagsel jtag selection input high permanent internal pull - down flash memory erase flash and nvm configuration bits erase command input high vddio reset state - erase input - internal pull - down enabled - schmitt trigger enabled (1) reset/test nrst synchronous microcontroller reset i /o low vddio permanent internal pull - up tst test select input permanent internal pull - down prime plc transceiver signal c ontroller agc automatic gain control output emitx plc transmission ports output see foot note (2) vnr plc zero crossing detection signal input afe_himp analog front - end high - impedance output rsta plc asynchronous reset input internal configuration: 33k typ. pull - down resistor rsts initialization signal input www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 13 table 3 - 1. signal description list (continued) signal name function type active level voltage reference comm e n ts prime plc transceiver configuration pins dbgx external configuration pins i/o see pin description for details intest intest12 external configuration pins i/o universal asynchronous receiver transceiver - uartx urxdx uart receive data input utxdx uart transmit data output pio controller - pioa - piob - pioc pa - pa31 parallel io controller a i /o vddio reset state - pio or system ios (2) - internal pull - up enabled - schmitt trigger enabled (1) pb - pb1 parallel io controller b i/o pc - pc31 parallel io controller c i/ o universal synchronous asynchronous receiver transmitter usartx sckx usartx serial clock i /o txdx usartx transmit data i/o rxdx usartx receive data input rtsx usartx reuest to send output ctsx usartx clear to send input synchronous serial controller - ssc t k ssc transmit clock i/o rk ssc receive clock i/o tf ssc transmit frame sync i/o timer/counter - tc tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o pulse width modulation controller - pwmc pwmhx pwm waveform output high for channel x output pwmlx pwm waveform output low for channel x output only output in complementary mode when dead time insertion is enabled pwmfi pwm fault input input www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 14 table 3 - 1. signal description list (continued) signal name function type active level voltage reference comm e n ts plc brigde intest1 intest external configuration pins i/o two - wire interface - twi twdx twix two - wire serial data i/o twckx twix two - wire serial clock i/o analog comparator - a cc ac - ac analog comparator input s analog usb full speed device dmm usb full speed data - analog, digital vddio reset state - usb mode - internal pull - down (3) dpp usb full speed data note: 1. schmitt triggers can be disabled through pio registers. 2. different configurations allowed depending on external topology and net behavior. 3. refer to usb section of the product electrical characteristics for information on pull - down value in usb mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 15 4. pin description table 4 - 1. pin description list pin number pin name functions type comments 1 advref analog analog voltage comparator reference 2, 3, 5, 29, 34, 46, 54, 57, 61, 74, 84, 91, 102, 110, 112, 124, 126 gnd power digital ground 4 agc output automatic gain control ? this digital output is managed by agc hardware logic to drive external circuitry if input signal attenuation is needed 6, 30, 58, 64, 70, 76, 85, 88, 87, 92, 103, 119, 120, vddio power digital power supply . voltage range: 3.0v - 3.6 v m ust be decoupled by external capacitors 7, 11 agnd power analog ground 8 pb0 pwmh0 ac 4 rtcout0 i/o pio controller b multiplexing (pb0): ? pwm waveform output high for channel 0 ? analog comparator input channel 4 ? programmable rtc waveform output ? se e signal description for details. 9, 12 avdd power a nalog converter power supply. voltage range: 3.0v - 3.6 v 10 pb1 pwmh1 ac 5 rtcout1 i/o pio controller b multiplexing (pb1): ? pwm waveform output high for channel 1 ? analog comparator input channel 5 ? programmable rtc waveform output ? se e signal description for details . 13 a vrh input analog input high voltage reference www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 16 table 4 - 1. pin description list (continued) pin number pin name functions type comments 14 pb2 urxd1 ac 6 wkup12 i/o pio controller b multiplexing (pb2): ? uart1 receive input data ? analog comparator input channel 6 ? wake - up source 12 ? fast start up of the processor ? active level: low 15 ainplc input direct - analog input voltage 16 pb3 utxd1 pck2 ac 7 i/o pio controller b multiplexing (pb3): ? uart1 transmit output data ? programmable clock output 2 ? analog comparator inp ut channel 7 ? se e signal description for details. 17 a vrl input analog input low voltage reference 18, 35 , 114, 116 vddin p voltage regulator input, analog comparator power supply . voltage range: 3.0v ? 3.6 v 19 vddout12 p voltage output regulator of 1.2 volts 20 pa17/pgmd5 td pck1 pwmh3 ac 0 i/o pio controller a multiplexing (pa17): ? synchronous serial controller (ssc) transmit output data ? programmable clock output 1 ? pwm waveform output high for channel 3 ? analog comparator input channel 0 ? se e signal description for details. 21 pc26 tioa4 i/o pio controller c multiplexing (pc26): ? tmer/counter channel 4 i/o line a ? general purpose i/o 22 pa18/pgmd6 rd pck2 ac 1 i/o pio controller a multiplexing (pa18): ? synchronous serial controller (ssc) receive input data ? programmable clock output 2 ? analog comparator input channel 1 ? se e signal description for details. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 17 table 4 - 1. pin description list (continued) pin number pin name functions type comments 23 pa21/pgmd9 rxd1 pck1 i/o pio controller a multiplexing (pa21): ? usart1 receive input data ? programmable clock output 1 ? se e signal description for details. 24, 45, 113 vddcore p core, embedded memories and the peripherals power supply : voltage range of 1.08v to 1.32v 25 pa19/pgmd7 rk pwml0 ac 2 wkup 9 i/o pio controller a multiplexing (pa19): ? synchronous serial controller (ssc) i/o receive clock ? pwm waveform output low for channel 0 ? analog comparator input channel 2 ? wake - up source 9 ? fast start up of the processor ? active level: low 26 pa22/pgmd10 txd1 i/o pio controller a multiplexing (pa22): ? usart1 transmit i/o data 27 pa23/pgmd11 sck1 pwmh0 piodcllk i/o pio controller a multiplexing (pa 23 ): ? usart1 i/o serial clock ? pwm waveform output high for channel 0 ? parallel capture mode input clock ? voltage reference: vddio 28 pa20/pgmd8 rf pwm l1 ac 3 wkup10 i/o pio controller a multiplexing (pa 20 ): ? synchronous serial controller (ssc) i/o receive frame sync ? pwm waveform output low for channel 1 ? analog comparator input channel 3 ? wake - up source 10 ? fast start up of the processor ? active level: low 31, 32, 37, 43, 44, nc - no connect www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 18 table 4 - 1. pin description list (continued) pin number pin name functions type comments 33 pc0 pwml0 i/o p io controller c multiplexing (pc0 ): ? pwm waveform output low for channel 0 ? general purpose i/o 36 pa16/pgmd4 tk tiob1 pwml2 wkup15 piodcen2 i/o p io controller a multiplexing (pa16 ): ? synchronous serial controller ( ssc ) i/o transmit clock ? timer/counter (tc) channel 1 i/o line b ? pwm waveform output low for channel 2 ? wake - up source 15 ? fast start up of the processor ? active level: low ? pio controller - parallel capture mode enable 2 ? voltage reference: vddio 38 pa15/pgmd3 tf tioa1 pwml3 wkup14 piodcen1 i/o p io controller a multiplexing (pa15 ): ? synchronous serial controller ( ssc ) i/o transmit frame sync ? timer/counter (tc) channel 1 i/o line a ? pwm waveform output low for channel 3 ? wake - up source 14 ? fast start up of the processor ? active level: low ? pio controller - parallel capture mode enable 1 ? voltage reference: vddio 39 intest1 o external configuration pin. this pin must connect to intest7 (pin 65) 40 intest2 o external configuration pin. this pin must connect to intest 8 (pin 63) 41 pa24/pgmd12 rts1 pwmh1 piodc0 i/o p io controller a multiplexing (pa24 ): ? usart1 request to send ? pwm waveform output high for channel 1 ? pio controller - parallel capture mode data 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 19 table 4 - 1. pin description list (continued) pin number pin name functions type comments 42 pc5 i/o p io controller c multiplexing (pc5 ): ? general purpose i/o 47 pa25/pgmd13 cts1 pwmh2 piodc1 i/o p io controller a multiplexing (pa25 ): ? usart1 clear to send ? pwm waveform output high for channel 2 ? pio controller - parallel capture mode data 1 48, 111 vdd out18 power 1.8v ldo output power supply. just requires output capacitor. not intended for external use 50 intest3 o external configuration pin. this pin must connect to intest 9 (pin 60) 5 1 intest4 o external configuration pin. this pin must connect to intest 10 (pin 66) 5 2 intest5 o external configuration pin. this pin must connect to intest 11 (pin 68) 5 3 pa10/pgmm2 utxd0 i/o p io controller a multiplexing (pa10 ): ? uart transmit output data ? 5 5 pa9/pgmm1 urxd0 pwmfi0 wkup6 i/o p io controller a multiplexing (pa9 ): ? uart receive input data ? pwm fault input ? wake - up source 6 ? fast start up of the processor ? active level: low 5 6 intest6 o external configuration pin. this pin must connect to intest 12 (pin 67) 59 pa8/ xout32 /pgmm0 cts0 wkup5 xout32 i/o p io controller a multiplexing (pa8 ): ? usart0 clear to send ? wake - up source 5 ? fast start up of the processor ? active level: low ? slow clock oscillator output ? se e signal description for details. 60 intest9 i external configuration pin. this pin must connect to intest 3 (pin 50) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 20 table 4 - 1. pin description list (continued) pin number pin name functions type comments 62 pa7/ xin32 /pgmnvalid rts0 pw mh3 xin32 i/o p io controller a multiplexing (pa7 ): ? usart0 request to send ? pwm waveform output high for channel 3 ? slow clock oscillator input ? se e signal description for details. 63 intest8 i external configuration pin. this pin must connect to intest 2 (pin 40) 65 intest7 i external configuration pin. this pin must connect to intest 1 (pin 39) 66 intest10 i external configuration pin. this pin must connect to intest 4 (pin 51) 67 intest12 i external configuration pin. this pin must connect to intest 6 (pin 56) 68 intest11 i external configuration pin. this pin m ust connect to intest5 (pin 52) 69 tdi/pb4 twd1 pwmh2 tdi i/o p io controller b multiplexing (pb4 ): ? two - wire interface ? twi1 two - wire i/o serial data ? pwm waveform output high for channel 2 ? serial wire/jtag debug port (swj - dp) test data in ? se e signal description for details. 71 pa6/pgmnoe txd0 pck0 i/o p io controller a multiplexing (pa6 ): ? usart0 transmit i/o data ? programmable clock output ? se e signal description for details. 72 pa5/pgmry rxd0 wkup4 i/o p io controller a multiplexing (pa5 ): ? usart0 receive input data ? wake - up source 4 ? fast start up of the processor ? active level: low www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 21 table 4 - 1. pin description list (continued) pin number pin name functions type comments 73 pa4/pgmncmd twck0 tclk0 wkup3 i/o p io controller a multiplexing (pa4 ): ? two - wire interface - twi0 two - wire i/o serial clock ? timer/counter (tc) channel 0 external clock input ? wake - up source 3 ? fast start up of the processor ? active level: low 75, 79, 80, 82, 86, 90, emit(1:6) output plc transmission ports . ? se e signal description for details. 77 nrst i/o synchronous prime plc reset ? se e signal description for details. 78 t st i test select ? se e signal description for details. 81 pa3 twd0 i/o p io controller a multiplexing (pa3 ): ? two - wire interface - twi0 two - wire i/o serial data 83 pa2/pgmen2 pwmh2 sck0 wkup2 i/o p io controller a multiplexing (pa2 ): ? pwm waveform output high for channel 2 ? usart0 i/o serial clock ? wake - up source 2 ? fast start up of the processor ? active level: low www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 22 table 4 - 1. pin description list (continued) pin number pin name functions type comments 93 afe_himp output analog front - end high - impedance ? this digital output is used by the chip to select between low - impedance and high - impedance transmission branch (when working with a ?two half - h - bridge branches? analog front end configuration). this way, the system adapts its transmission external circuitry to the net impedance, improving transmission behavior. the polarity of thi s pin can be inverted by hardware. please refer to the reference design for further information. 94 pa1/pgmen1 pwmh1 tiob0 wkup1 i/o p io controller a multiplexing (pa1 ): ? pwm waveform output high for channel 1 ? timer/counter (tc) channel 0 i/o line b ? wake - up source 1 ? fast start up of the processor ? active level: low 95 pa0/pgmen0 pwmh0 tioa0 wkup0 i/o p io controller a multiplexing (pa0 ): ? pwm waveform output high for channel 0 ? timer/counter (tc) channel 0 i/o line a ? wake - up source 0 ? fast start up of the processor ? active level: low 96 vnr input plc zero crossing detection signal ? this input detects the zero - crossing of the mains voltage, needed to determine proper switching times. depending on whether an isolated or a non - isolated power supply is being used, isolation of this pin should be taken into account in the circuitry design. please refer to the reference design for further information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 23 table 4 - 1. pin description list (continued) pin number pin name functions type comments 97 tdo/ traceswo /pb5 twck1 pwml0 wkup13 tdo traceswo i/o p io controller b multiplexing (pb5 ): ? two - wire interface - twi1 two - wire i/o serial clock ? pwm waveform output low for channel 0 ? wake - up source 13 ? fast start up of the processor ? active level: low ? tdo - test data out / trace asynchronous data out ( traceswo ) ? se e signal description for details. 98 dbg0 input internal configuration: must connect n w \ s s x o o - up resistor 99 jtagsel a - i analog input used to select the jtag boundary scan when asserted at a high level. ? se e signal description for details. 100 dbg1 input , q w h u q d o f r q i l j x u d w l r q p x v w n w \ s s x o o - up resistor 101 dbg2 output no connect 104 dbg3 input , q w h u q d o f r q i l j x u d w l r q p x v w n w \ s s x o o - up resistor 105 tms/ swd io/pb6 tms swd io i/o p io controller b multiplexing (pb6 ): ? tms - test mode input select / ( swd io ) serial wire i/o ? se e signal description for details. 106 dbg4 input no connect 107 rsta input plc asynchronous reset ? rsta is a digital input pin used to perform a hardware reset of the asic ? rsta is active high www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 24 table 4 - 1. pin description list (continued) pin number pin name functions type comments 108 rsts input initialization signal ? during power - on, d_init should be released before asynchronous reset signal rsta, in order to ensure proper system start up. not minimum time is required between both releases, w ! ? d_init is active high 109 tck / swclk / pb7 tck swclk i/o pio controller b multiplexing (pb7): ? tck - test clock/(swclk) serial wire clock ? se e signal description for details. 115 erase /pb12 pwml1 erase i/o pio controller b multiplexing (pb12): ? pwm waveform output low for channel 0 ? flash and nvm configuration bits erase command ? se e signal description for details. 117 ddm /pb10 dm m a - i/o p io controller b multiplexing (pb10 ): ? usb full speed data ? ? se e signal description for details. 118 ddp /pb11 dp p a - i/o p io controller b multiplexing (pb11 ): ? usb full speed data + ? se e signal description for details. 121 plc_clockin input external clock reference ? plc_clockin must be connected to one terminal of a crystal (when a crystal is being used) or tied to ground if a compatible oscillator is being used www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 25 table 4 - 1. pin description list (continued) pin number pin name functions type comments 123 plc_clockout i/o external clock reference ? plc_clockout must be connected to one terminal of a crystal (when a crystal is being used) or to one terminal of a compatible oscillator (when a compatible oscillator is being used) 125 pb8/xout xout output pio controller b multiplexing (pb8): ? main oscilator output 127 pb9/pgmck/xin xin input pio controller b multiplexing (pb9): ? main oscilator input 128 vddpll power oscillator and pll power supply ? 1.08v to 1.32v www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 26 5. power considerations 5.1 power supplies the sam4sp32a has several types of power supply pins: ? vddcore pins: power the core, the embedded memories and the peripherals. voltage ranges from 1.08v to 1.32v. ? vddio pins: power the peripherals i/o lines (input/output buffers), usb transceiver, backup part, 32 khz crystal oscillator and oscillator pads. v oltage ranges from 3.0v to 3.6v. ? vddin pin: voltage regulator input, and analog comparator power supply. voltage ranges from 3.0 v to 3.6v. ? vddpll pin: powers the plla, pllb, the fast rc and the 3 to 20 mhz oscillator. voltage ranges from 1.08v to 1.32v. ? avdd pin: prime plc analog converter power supply. voltage ranges from 3.0 v to 3.6v. 5.2 voltage regulator the sam4sp32a embeds two voltage regulator s that are managed by the supply controller. the first internal regulator is designed to supply the internal core of sam4sp32a it features two operating modes: ? , q 1 r u p d o p r g h w k h y r o w d j h u h j x o d w r u f r q v x p h v o h v v w k d q $ v w d w l f f x u u h q w d q g g u d z v p $ r i r x w s x w current. internal adaptive biasing adjusts the regulator quiescent current depending on the require d load f x u u h q w , q : d l w 0 r g h t x l h v f h q w f x u u h q w l v r q o \ $ ? , q % d f n x s p r g h w k h y r o w d j h u h j x o d w r u f r q v x p h v o h v v w k d q $ z k l o h l w v r x w s x w 9 ' ' 2 8 7 12 ) is driven internally to gnd. the default output voltage is 1.20v and the start - up time to reach normal m ode is less w k d q v the second internal regulator is designed to supply the internal prime plc transceiver . its output (vddout18) is driven internally to gnd and the default output voltage is 1.8v. the vddout18 pin just requires an output capacitor i q w k h u d q j h r i ) - ) and it is not intended for external use. for adequate input and output power supply decoupling/bypassing, refer to the ?voltage regulator? section in the ?electrical characteristics? section of the datasheet. 5.3 typical powering s chematics the sam4sp32a supports a 3.0 v - 3.6v single supply mode. the internal regulator input is con nected to the source and its output feeds vddcore. figure 5 - 1 shows the power schematics. as vddin powers the voltage reg ulator, and the analog comparator, when the user does not want to use the embedded voltage regulator, it can be disabled by softwar e via the supc (note that this is different from backup mode). www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 27 figure 5 - 1. single supply note: restrictions for usb, vddio needs to be greater than 3.0v. figure 5 - 2. core externally supplied m ain supply (3.0 v -3.6 v ) a nalog c ompa r a t o r . usb t r ans c ei v er s . vddin v oltage r egul a t or vddout12 vdd c ore vddio vddpll m ain supply (3.0 v -3.6 v ) c an be the same supply vdd c ore supply (1.08 v -1.32 v ) pl c t r ans c ei v er a nalog c ompa r a t or supplies (3.0 v -3.6 v ) a nalog c ompa r a t or usb t r ans c ei v er s . vddin v oltage r egul a t or vddout12 vdd c ore vddio vddpll prime p l c t r ans c ei v er www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 28 figure 5 - 3. backup baterry a nalog c ompa ra t or usb t r ans c ei v er s . vddin v oltage r egul a t or 3.3v ldo bac k up ba tt er y + - on/off in out vddout12 m ain supply vdd c ore prime p l c a nalog c ompa r a t or supplies (3.0 v -3.6 v ) vddio vddpll pi o x ( o utput) w akeupx e x t e r nal w akeup si g nal no t e: t he t w o diodes p r o vide a swi t ch o v er ci r cui t ( f or illust ra tion pu r pose) be t w een the bac k up b a tt er y and the main supply when the s y st em is put in bac k up mod e . prime p l c t r ans c ei v er www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 29 5.4 active mode active mode is the normal running mode with the core clock r unning from the fast rc oscilla tor, the main crystal oscillator or the plla. the power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 low - power modes in low - power mode, the 3. 3 volts power source must be shu t down before running in any low - power mode. the prime plc transceiver peripheral is turn ed off during a low - power mode configuration. the various low - power modes of the sam4sp32a are described below: 5.5.1 backup mode the purpose of backup mode is to achieve the lowest power co nsumption possible in a sys tem which is performing periodic wake - ups to perform tasks but not requiring fast startup time. the supply controller, zero - power power - on reset, rtt, rtc, backup registers and 32 khz oscillator (rc or crystal os cillator selected by software in the supply controller) are running. the regulator s , prime plc transceiver and the core supply are off. backup mode is based on the cortex - m4 deep sleep mode with the voltage regulator s disabled. the sam4sp32a can be awake ned from this mode through wup0 - 15 pins, the supply monitor (sm), the rtt or rtc wake - up event. backup mode is entered by using bit vroff of supply controller (supc_cr) and with the sleepdeep bit in the cortex - m4 system control regist er set to 1. entering backup mode : ? set the sleepdeep bit of cortex_m4, set to 1. ? set the vroff bit of supc_cr at 1 exit from backup mode happens if one of the following enable wake up events occurs: ? wkupen0 - 15 pins (level transition, configurable debouncing) ? supply monitor alarm ? rtc alarm ? rtt alarm 5.5.2 wait mode the purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less t k d q i h z k x q g u h g v & x u u h q w & r q sumption in wait mode l v w \ s l f d o o \ i h z $ (total current consumption) if the internal voltage regulator is used. in this mode, the clocks of the core, peripherals and memories are stopped. however, the core, peripherals and memories power supplies are still powered except for the prime plc transceiver which remains turn ed off . from this mode, a fast start up is available. this mode is entered via waitmode =1 (waitmode bit in ckgr_mor) and with lpm = 1 (low power mode bit in pmc_fsmr) and with flpm = 00 or flpm=01 (flash low p ower mode bits in pmc_fsmr) . the cortex - m4 is able to handle external events or internal events in order to wake - up the core. this is done by configuring the external lines wup0 - 15 as fast startup wake - up pins (refer to 0 ). rtc or rtt alarm and usb wake - up events can be used to wake up the cpu. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 30 entering wait mode: ? select the 4/8/12 mhz fast rc oscillator as main cl ock ? set the lpm bit in the pmc fast startup mode register (pmc_fsmr) ? set the flpm bitfield in the pmc fast startup mode register (pmc_fsmr) ? set flash wait state at 0 ? set the waitmode bit = 1 in pmc main oscillator register (ckgr_mor) ? wait for master c lock ready mckrdy=1 in the pmc status register (pmc_sr) note: internal main clock resynchronization cycles are necessary between the writing of moscrcen bit and the effective entry in wait mode. depending on the user application, waiting for moscrcen bit to be cleared is recommended to ensure that the core will not execute unde - sired instructions. 5.5.3 sleep mode the purpose of sleep mode is to optimize power consumption of the device versus response time. in this mode, only the core clock is stopped. the peri pheral clocks can be enabled. the current consumption in this mode is application dependent. this mode is entered via wait for interrupt (wfi) with lpm = 0 in pmc_fsmr. the processor can be awakened from an interrupt if wfi instruction of the cortex m4 is used. 5.5.4 low power mode summary table the modes detailed above are the main low - power modes. each part can be set to on or off separately and wake up sources can be indivi dually configured. table 5 - 1 shows a summary of the configurations of the low - power modes. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 31 table 5 - 1. low power mode configuration summary mode supc, 32 khz o scillator, rtc, rtt backup registers, por (backup region) regulator core memory periphericals mode entry potential wake up sources core at wake up pio state while in low power mode pio state at wake up consumption (2) (3) wake - up time (1) backup mode on off off (not powered) vroff 1 sleepdeep bit 1 wup - 1 pins sm alarm rtc alarm rtt alarm reset previous state saved pioa piob pioc inputs with pull ups 1.5 a typ ms wait mode on on powered (not clocked) waitmode1 sleepdeep bit lpm bit 1 any event from fast startup through wup - 1 pins rtc alarm rtt alarm usb wake - up clocked back previous state saved unchanged 15 a/ 25 a < 10 s sleep mode on on powered (1) (not clocked) wfe or wfi sleepdeep bit lpm bit entry mode wfi interrupt only any enabled interrupt clocked back previous state saved unchanged () () note: 1. when considering wake - up time, the time required to start the pll is not taken into account. once started, the device works with the 4/8/12 mhz fast rc oscillator. the user has to add the pll start - up time if it is needed in the system. the wake - up time is defined as the time taken for wake up until the first instruction is fetched. 2. the external loads on pios are not taken into account in the calculation. 3. supply monitor current consumption is not included. 4. total current consumption. 5. $ r q 9 ' ' & 2 5 ( $ i r u w r w d o f x u u h q w f r q v x p s w l r q x v l q j l q w h u q d o y r o w d j h u h j x o d w r u $ i r u w r w d o current consump - tion (without using internal voltage regulator). 6. depends on mck frequency. 7. in this mode the core is supplied and not clocked but some peripherals can be clocked. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 32 5.6 wake - up sources the wake - up events allow the device to exit the backup mode. when a wake - up event is detected, the supply controller performs a sequence which automatically re - enables the core power supply and the sram power supply, if they are not already enabled. figure 5 - 4. wake - up sources wkup15 wkupen15 wkupt15 wkupen1 wkupen0 d eboun c er sl ck wkupdbc wkups r t cen r t c_ala r m smen sm_out c or e supply r esta r t wkupis0 wkupis1 wkupis15 f alling/ r ising e dge d e t e c t or wkupt0 f alling/ r ising e dge d e t e c t or wkupt1 f alling/ r ising e dge d e t e c t or wkup0 wkup1 r t ten r tt_ala r m www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 33 5.7 fast startup the sam4sp32a allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. a fast start up can occur upon detection of a low level on one of the 19 wake - u p inputs (wkup0 to 15 + sm + rtc + rtt). the fast restart circuitry, as shown in figure 5 - 5 , is fully asynchronous and provides a fast start - up sig nal to the power management controller. as soon as the fast start - up signal is asserted, the pmc automatically restarts the embedded 4/8/12 mhz fast rc oscillator, switches the master clock on this 4 mhz clock and reenables the processor clock. figure 5 - 5. fast start - up sources fast_ r esta r t wkup15 fs t t15 fstp15 wkup1 fs t t1 fstp1 wkup0 fs t t0 fstp0 r t t al r t c al usbal r t t a la r m r t c a la r m usb a la r m www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 34 6. input/output lines the sam4sp32a has several kinds of input/output (i/o) lines such as general purpose i/os (gpio) and system i/os. gpios can have alternate functionality due to multiplexing capabilities of the pio controllers. the same pi o line can be used whether in i/o mode or by the multiplexed peripheral. system i/os include pins such as test pins, oscillators, erase or analog inputs. 6.1 general purpose i/o lines gpio lines are managed by pio controllers. all i/os have several input or ou tput modes such as pull - up or pull - down, input schmitt triggers, multi - drive (open - drain), glitch filters, debouncing or input change interrupt. programming of t hese modes is performed indepen dently for each i/o line through the pio controller user interface. for more details, refer to the product ?pio controller? section. the input/output buffers of the pio lines are supplied through vddio power supply rail. the sam4sp32a embeds high speed p ads able to handl e up to 45 mhz for plc bridge clock lines and 35 mhz on other lines. see ac characteristics section of the datasheet for more details. typical pull - up and pull - down value is 100 k ? for all i/os. each i/o line also embeds an odt (on - die te rmination), (see figure 6 - 1 below). it consists of an internal series resistor termination scheme for impedance matching between the out - put ( sam4s p32a ) driver and the pcb trace impedance preventing signal reflection. the series resistor helps to reduce ios switching current (di/dt) thereby reducing in turn, emi. it also decreases overshoot and undershoot (ringing) due to inductance of interconnect b etween devices or between boards. in conclusion odt helps diminish signal integrity issues. figure 6 - 1. on - die termination 6.2 system i/o lines system i/o lines are pins used by oscillators, test mode, reset, jtag, and the like. described below in table 6 - 1 are the sam4sp32a system i/o lines shared with pio lines. these pins are software configurable as general purpose i/o or system pins. at s tartup the default function of these pins is always used. pcb t r a c e z0 ~ 50 ohms r e c ei v er s a m4 d r i v er with r odt z out ~ 10 ohms z0 ~ z out + r odt o d t 36 ohms t y p . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 35 table 6 - 1. system i/o configuration pin list system_io bit number default function after reset other functions constraints for normal start configuration 12 erase pb12 low level at startup (1) in matrix user interface registers (refer to the system i/o configuration register in the bus matrix section of the datasheet) 1 dmm pb1 - 11 dpp pb11 - tck/swclk pb - tms/swdio pb - tdo/traceeswo pb - tdi pb - - pa xin32 - see footnote (2) below - pa xout32 - - pb xin - see footnote (3) below - pb xout - note: 1. if pb12 is used as pio input in user applications, a low level must be ensured at startup to prevent flash erase before the user application sets pb12 into pio mode, 2. in the product datasheet refer to: ?slow clock generator? of the ?supply controller? sect ion. 3. in the product datasheet refer to: ?3 to 20 mhz crystal oscillator? information in the ?pmc? section 6.2.2 serial wire jtag debug port (swj - dp) pins the swj - dp pins are tck/swclk, tms/swdio, tdo/swo, tdi and commonly provided on a standard 20 - pin jtag connector defined by arm. for more details about voltage refer - ence and reset state, refer to table 3 - 1 . at startup, swj - dp pins are configured in swj - dp mode to allow connection with debugging probe. please refer to the ?debug and test? section of the product datasheet. swj - dp pins can be used as standard i/os to provide users more general input/outp ut pins when the debug port is not needed in the end application. mode selection between swj - dp mode (system io mode) and general io mode is performed through the ahb matrix special function registers (matrix_sfr). configuration of the pad for pull - up, tri ggers, debouncing and glitch filters is possible regardless of the mode. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. it integrates a permanent pull - down resistor of about 15 k ? to gnd, so that it can be left unco nnected for normal operations. by default, the jtag debug port is active. if the debugger host wants to switch to the serial wire debug port, it must provide a dedicated jtag sequence on tms/swdio and tck/swclk which disables the jtag - dp and enables the s w - dp. when the serial wire debug port is active, tdo/traceswo can be used for trace. the asynchronous trace output (traceswo) is multiplexed with tdo. so the asynchro - nous trace can only be used with sw - dp, not jtag - dp. for more information about sw - dp an d jtag - dp switching, please refer to the ?debug and test? section. 6.3 test pin the tst pin is used for jtag boundary scan manufacturing test or fast flash programming mode of the sam4sp32a series. the tst pin integrates a permanent pull - down resistor of about 15 k ? to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, see the fast flash programming interface (ffpi) section. for more on the manufacturing and test mode, refer to the ?debug and test? section of the prod uct datasheet. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 36 6.4 nrst pin the nrst pin is bidirectional. it is handled by the on - chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. it will reset the core and the peripherals except the backup region (rtc, rtt and supply controller). there is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length. the nrst pin integrates a permanent pull - up resistor to vd dio of about 100 k ? . by default, the nrst pin is configured as an input. 6.5 erase pin the erase pin is used to reinitialize the flash content (and some of its nvm bits) to an erased state (all bits read as logic level 1). it integrates a pull - down resistor of about 100 k ? to gnd, so that it can be left unconnected for normal operations. this pin is debounced by sclk to improve the glitch tolerance. when the erase pin is tied high during less than 100 ms, it is not taken into account. the pin must be tied high during more than 220 ms to perform a flash erase operation. the erase pin is a system i/o pin and can be used as a standard i/o. at startup, the erase pin is not configured as a pio pin. if the erase pin is used as a standard i/o, startup level of this p in must be low to prevent unwanted erasing. refer to peripheral signal multiplexing on i/o lines also, if the erase pin is used as a standard i/o outp ut, asserting the pin to low does not erase the flash. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 37 7. processor and architecture 7.1 arm cortex - m4 processor ? thumb - 2 (isa) subset consisting of all base thumb - 2 instructions, 16 - bit and 32 - bit. ? harvard processor architecture enabling simultaneous instruction fetch with data load/store. ? three - stage pipeline. ? single cycle 32 - bit multiply. ? hardware divide. ? thumb and debug states. ? handler and thread modes. ? low latency isr entry and exit. 7.2 apb/ahb bridge the sam4sp32a embeds one peripheral bridge: the peripherals of the bridge are clocked by mck. 7.3 matrix master the bus matrix of the sam4sp32a manages 4 masters, which means that each master shall perform an access concurrently with others, to an available slave. each master has its own decoder, which is defined specifically for each master. in order to simplify the addressing, all the masters have the same decodings. table 7 - 1. list of bus matrix masters master 0 cortex - m4 instruction/data master 1 cor tex - m4 system master 2 peripheral dma controller (pdc) master 3 crc calculation unit 7.4 matrix slaves the bus matrix of the sam4sp32a manages 5 slaves. each slave has its own arbiter, allowing a different arbitration per slave. table 7 - 2. list of bus matrix slaves slave 0 internal sram slave 1 internal rom slave 2 internal flash slave 3 external bus interface slave 4 peripheral bridge www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 38 7.5 master to slave access all the masters can normally access all the slaves. however, some paths do not make sense, for example allowing access from the cortex - 43 s bus to the internal rom. thus, these paths are forbidden or simply not wired, and shown as ? - ? in the following table. table 7 - 3. sam4sp32a master to slave access slaves masters 1 2 3 cortex - m i/d bus cortex - m s bus pdc crccu internal sram - x x x 1 internal rom x - x x 2 internal flash x - - x 3 external bus interface - x x x peripherical bridge - x x - 7.6 peripherical dma controller ? handles data transfer between peripherals and memories ? low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory ? next pointer management for reducing interrupt latency requirement the periphera l dma controller handles transfer requests from the channel according to the following priorities (low to high priorities): table 7 - 4. peripherical dma controller in s tance name channel t/r pwm transmit twi1 transmit twi transmit uart1 transmit uart transmit u sart1 transmit u sart transmit plc bridge transmit ssc transmit www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 39 table 7 - 5. peripherical dma controller in s tance name channel t/r pioa receive twi1 receive twi receive uart1 receive uart receive u sart1 receive u sart receive plc bridge receive ssc receive 7.7 debug and test features ? debug access to all memory and registers in the system, including cortex - m 4 register bank when the core is running, halted, or held in reset. ? serial wire debug port (sw - dp) and serial wire jtag debug port (swj - dp) debug ac cess ? flash patch and breakpoint (fpb) unit for implementing breakpoints and code patches ? data watchpoint and trace (dwt) unit for implementing watch points, data tracing, and system profiling ? instrumentation trace macrocell (itm) for support of printf s tyle debugging ? ieee?1149.1 jtag boundary scan on all digital pins www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 40 8. sam4sp32a product mapping figure 8 - 1. sam4sp32a product mapping a dd r ess memo r y spa c e c ode 1 m b yt e bit band r eg iion 1 m b yt e bit band r eg iion 1 m b yt e bit band r eg iion 0x00000000 sr a m 0x20000000 0x20100000 0x20400000 0x24000000 0x40000000 offset id pe r iphe r al block c ode b oot m emo r y 0x00000000 0x00400000 0x00800000 r ese r v ed 0x00c00000 0x1fffffff p er iphe r als r ese r v ed 18 0x40000000 ssc 22 0x40004000 r ese r v ed 21 0x40008000 0x4000c000 tc0 t c0 0x40010000 23 tc0 t c1 +0x40 24 tc0 t c2 +0x80 25 tc1 t c3 0x40014000 26 tc1 t c4 +0x40 27 tc1 t c5 +0x80 28 t wi0 19 0x40018000 t wi1 20 0x4001c000 pwm 31 0x40020000 usa r t0 usa r t1 14 0x40024000 15 0x40028000 0x4002c000 r ese r v ed r ese r v ed 0x40030000 udp 33 0x40034000 r ese r v ed 29 0x40038000 r ese r v ed 30 0x4003c000 a c c 34 0x40040000 cr c cu 35 0x40044000 0x40048000 s y st em c on tr oller 0x400e0000 0x400e2600 0x40100000 0x40200000 0x40400000 0x60000000 ex t er nal r a m smc chip s ele c t 0 0x60000000 smc chip s ele c t 1 undefined 32 m b yt es bit band alias 0x61000000 smc chip s ele c t 2 0x62000000 smc chip s ele c t 3 0x63000000 0x64000000 0x9fffffff s y st em c on tr oller smc 10 0x400e0000 m a trix 0x400e0200 p mc 5 0x400e0400 u ar t0 u ar t1 8 0x400e0600 chipid 0x400e0740 9 0x400e0800 efc 6 0x400e0a00 0x400e0c00 pi o a 11 0x400e0e00 piob 12 0x400e1000 pioc 13 0x400e1200 rs t c 0x400e1400 1 supc +0x10 r t t +0x30 3 wd t +0x50 4 r t c +0x60 2 gpbr +0x90 0x400e1600 0x4007ffff i n t er nal f lash i n t er nal r om r ese r v ed p er iphe r als ex t er nal s r a m 0x60000000 0xa0000000 s y st em 0xe0000000 0xffffffff r ese r v ed r ese r v ed efc1 r ese r v ed r ese r v ed r ese r v ed r ese r v ed 32 m b yt es bit band alias r ese r v ed www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 41 9. memories 9.1 embedded memories 9.1.1 internal sram the sam4sp32a device embeds a total of 160 - kbytes high - speed sram. the sram is accessible over system cortex - m4 bus at address 0x2000 0000. the sram is in the bit band region. the bit band alias region is from 0x2200 0000 to 0x23ff ffff. 9.1.2 internal rom the sam4sp32a embeds an internal rom, which contains the sam boot assistant (sam - ba?), in appli cation programming routines (iap) and fast flash programming interface (ffpi). at any time, the rom is mapped at address 0x0080 0000. 9.1.3 embedded flash 9.1.3.1 flash overview flash size is 2x1024 kbytes . the memory is organized in sectors. each sector has a size of 64 kbytes. the first sector of 64 kbytes is divided into 3 smaller sectors. the three smaller sectors are organized to consist of 2 sectors of 8 kbytes and 1 sector of 48 kbytes. refer to 41 below. figure 9 - 1. global flash organization small s ec t or 0 8 k b yt es small s ec t or 1 8 k b yt es la r ger s ec t or 48 k b yt es s ec t or 1 64 k b yt es 64 k b yt es s ec t or n s ec t or 0 s ec t or si z e s ec t or name www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 42 each sector is organized in pages of 512 bytes. for sector 0: ? the smaller sector 0 has 16 pages of 512bytes ? the smaller sector 1 has 16 pages of 512 bytes ? the larger sector has 96 pages o f 512 bytes from sector 1 to n: the rest of the array is composed of 64 kbytes sector of each 128 pages of 512bytes. refer to figure 9 - 2 below. figure 9 - 2. flash sector organization ? sam4sp32a : the flash size is 2 x 1024 kbytes ? internal flash0 address is 0x0040_0000 ? internal flash1 address is 0x0050_0000 refer to figure 9 - 3 below for the organization of the flash following its size. s ec t or 0 s ec t or 1 smaller se c t or 0 smaller se c t or 1 la r ger se c t or a se c t or si z e is 64 k b yt es 16 pages of 512 b yt es 16 pages of 512 b yt es 96 pages of 512 b yt es 128 pages of 512 b yt es s ec t or n 128 pages of 512 b yt es www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 43 figure 9 - 3. flash size erasing the memory can be performed as follows: ? on a 512 - byte page inside a sector, of 8k bytes (1) note: ewp and ewpl commands can be only used in 8 kbytes sectors. ? on a 4 - kbyte block inside a sector of 8 kbytes/48 kbytes/64 k b ytes ? on a sector of 8 kbytes/48 kbytes/64 kbytes ? on chip the memory has one additional reprogrammable page that can be used as page signature by the user. it is accessible through specific modes, for erase, write and read operations. erase pin assertion will not erase the user signature page. erase memory by page is possible only in sector of 8 kbytes. (1) ewp and ewpl commands can be o nly used in sector 8kbytes sectors. 9.1.3.2 enhanced embedded flash controller the enhanced embedded flash controller (hefc4) manages accesses performed by the masters of the system. it enables reading the flash and writin g the write buffer. it also con tains a use r interface, mapped on the apb. the enhanced embedded flash controller ensures the interface of the flash block. it manages the programming, erasing, locking and unlocking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the sys - tem about the flash organization, thus making the software generic. 9.1.3.3 flash speed the user needs to set the number of wait states depending on the frequency used: for more details, refer to the ? ac characteristics? sub - section of the product ?electrical characteristics?. 2 x 8k b yt es 1 x 48k b yt es 15 x 64k b yt es f lash 1 m b yt es www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 44 9.1.3.4 lock regions several lock bits are used to protect write and erase operations on lock regions. a lock region is composed of several consecutive pages, and each lock region has its associated lock bit. table 9 - 1. lock bit number product number of lock bits lock region size samsp32a 2 (12 12) kbytes if a locked - region?s erase or program command occurs, the command is aborted and the eefc triggers an interrupt. the lock bits are software programmable through the eefc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 9.1.3.5 security bit fe ature the sam4sp32a features a security bit, based on a specific general purpose nvm bit (gpnvm bit 0). when the security is enabled, any access to the flash, sram, core registers and internal peripherals either through the ice interface or through the fas t flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. this security bit can only be enabled, through the command ?set general purpose nvm bit 0? of the eefc user interface. disabling the security bit can only be achieved by asserting the erase pin at 1, and after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash, sram, core registers, internal peripherals are permitted. it is important to note that t he assertion of the erase pin should always be longer than 200 ms. as the erase pin integrates a permanent pull - down, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd for the final application. 9.1.3.6 calibra tion bits nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the calibration bits. 9.1.3.7 unique identifier sam4sp32a device integrate s its own 128 - bit unique identifier. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the unique identifier. 9.1.3.8 user signature each part contains a user signature of 512 bytes. it can be used by the user to s tore user information such as trimming, keys, etc., that the customer does not want to be erased by asserting the erase pin or by software erase command. read, write and erase of this area are allowed. 9.1.3.9 fast flash programming interface the fast flash progra mming interface allows programming the device through either a serial jtag interface or through a multiplexed fully - handshaked parallel port. it allows gang programming with market - standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when tst and pa0 and pa1are tied low. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 45 9.1.3.10 sam - ba boot the sam - ba boot is a default boot program which provides an easy way to program in - situ the on - chip flash memory. the sam - ba boot assistant supports serial communication via the uart and usb. the sam - ba boot provides an interface with sam - ba graphic user interface (gui). the sam - ba boot is in rom and is mapped in flash at address 0x0 when gpnvm bit 1 is set to 0. 9.1.3.11 gpnvm bits the gpnvm bits of the sam4sp32a are only available on flash0. there is no gpnvm bit on flash1. the gpnvm0 is the security bit. the gpnvm1 is used to select the boot mode (boot always at 0x00) on rom or flash. the sam4sp32a embeds an additional gpnvm bit : gpnvm2. this gpnvm bit is used only to swap the flash0 and flash1. if gpnvm bit 2 is: enable: if the flash1 is mapped at address 0x0040_0000 (flash1 and flash0 are continuous). disable: if the flash0 is mapped at address 0x0040_0000 (flash0 and flash1 are continuous). table 9 - 2. general purpose non volatile memory bits gpnvmbit[#] function security bit 1 boot mode selection 2 flash selection (flash or flash 1) 9.1.4 boot strategies the system always boots at address 0x0. to ensure maximum boot possibilities, the memory layout can be changed via gpnvm. a general purpose nvm (gpnvm) bit is used to boot either on the rom (default) or from the flash. the gpnvm bit can be cleared or set respectively through the commands ?clear general - purpose nvm bit? and ?set general - purpose nvm bit? of the eefc user interface. setting gpnvm bit 1 selects the boot from the flash, clearing it selects the boot from the rom. asserting erase clears the gpnvm bit 1 and thus selects the boot from the rom by default. setting the gpnvm bit 2 selects bank 1, clearing it selects the boot from bank 0. asserting erase clears the gpnvm bit 2 and thus selects the boot from bank 0 by default. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 46 10. system controller th e system controller is a set of peripherals, which allow hand ling of key elements of the sys tem, such as power, resets, clocks, time , interrupts, watchdog, etc figure 10 - 1. system controller block diagram s o f t w a r e c o n t r olled v oltage r egul a t or m a t r ix s r a m w a t chdog t imer c o r t e x -m4 f lash p e r iphe r als p e r iphe r al b r idge z e r o - p o w er p o w e r - on r eset supply m oni t or (bac k u p ) r t c p o w er m anageme n t c o n t r oller embedded 32 k h z r c oscill a t or xtal 32 k h z oscill a t or supply c o n t r oller b r o wnout d e t e c t or ( c o r e) r eset c o n t r oller bac k up p o w er supply c o r e p o w er supply plla vr_on vr_mode on out r t c_ala r m s l ck r t c_n r eset p r oc_n r eset pe r iph_n r eset i c e_n r eset m as t er clock mck s l ck nrst m ainck fs t t0 - fs t t15 xin32 x out32 osc32k_ x tal_en sl o w clock s l ck osc32k_ r c_en vddio vdd c ore vddout12 advref wkup0 - wkup15 bod_ c o r e_on l c o r e_b r o wn_out r t t r tt_ala r m s l ck r tt_n r eset xin x out vddio vddin pi o x usb t r ansei v ers vddio ddp ddm m ainck d a c a nalog c i r cuit r y pllb pllbck pll a ck e m b e d d e d 1 2 / 8 / 4 m h z r c o s c il l a t o r m ain clo c k m ainck s l ck 3 - 20 m h z x t al oscill a t or vddio x t alsel g ene r al p u r pose ba c k up r e g is t ers v dd c o r e_n r eset v dd c o r e_n r eset pi o a/b/c i nput/ o utput bu ff ers adc a nalog c i r cuit r y a nalog c ompa r a t or fs t t0 - fs t t15 a r e possible f ast s ta r tup sou r c e s , gene r a t ed b y wkup0 - wkup15 pin s , but a r e not p h y sical pin s . adc ch. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 47 10.1 system controller and peripherals mapping please refer to sam4sp32a product mapping . all the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 power - on - reset, brownout and supply monitor the sam4sp32a embeds three features to monitor, warn and/or reset the chip: ? power - on - reset on vddio ? brownout detector on vddcore ? supply monitor on vddio 10.2.1 power - on-reset the power - on - reset monitors vddio. it is always activated and monitors voltage at start up but also during power down. if vddio goes below the threshold voltage, the entire chip is reset. for more information, refer to the electrical characteristics section of the datasheet. 10.2.2 brownout detector on vddcore the brownout detector monitors vddcore. it is active by default. it can be deactivated b y software through the supply controller (supc_mr). it is especially recommended to disable it during low - power modes such as wait or sleep modes. if vddcore goes below the threshold voltage, the reset of the core is asserted. for more information, refer to the supply controller (supc) and electrical characteristics sections of the datasheet. 10.2.3 supply monitor on vddio the supply monitor monitors vddio. it is not active by default. it can be activated by software and is fully programmable with 16 step s for th e threshold (between 3.0 v to 3.6 v ). it is controlled by the supply controller (supc). a sample mode is possible. it allows dividing the supply monitor power consumption by a factor of up to 2048. for more information, refer to the supc and electrical cha racteristics sections of the datasheet. 10.3 reset controller the reset controller is based on a power - on - reset cell, and a supply monitor on vddcore. the reset controller is capable to return to the software the source of the last reset, either a general reset, a wake - up reset, a software reset, a user reset or a wa tchdog reset. the reset controller controls the internal resets of the system and the nrst pin input/output. it is capable to shape a reset signal for the external devices, simplifying to a minimum connec tion of a push - button on the nrst pin to implement a manual reset. the configuration of the reset controller is saved as supplied on vddio. 10.4 supply controller (supc) the supply controller controls the power supplies of each section of the processor and the peripherals (via voltage regulator control). the sup ply controller has its own reset circuitry and is clocked by the 32 khz slow clock generator. the reset circuitry is based on a zero - power power - on reset cell and a brownout detector cell. the zero - power power - on reset allows the supply controller to start properly, while the soft - ware - programmable brownout detector allows detection of either a battery discharge or main voltage loss. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 48 the slow clock generator is based on a 32 khz crystal oscillator and an embedded 32 khz rc oscillator. the slow clock defaul ts to the rc oscillator, but the software can enable the crystal oscillator and select it as the slow clock source. the supply controller starts up the device by sequentially enabling the internal power switches and the voltage regulator, then it generate s the proper reset signals to the core power supply. it also enables to set the system in different low - power modes and to wake it up from a wide range of events. 10.5 clock generator the clock generator is made up of: ? one low - power 32768hz slow clock oscilla tor with bypass mode ? one low - power rc oscillator ? one 3 - 20 mhz crystal oscillator, which can be bypassed ? one fast rc oscillator, factory programmed. three output frequencies can be selected: 4, 8 or 12 mhz. by default 4 mhz is selected. ? one 80 to 240 mh z pll (pllb) providing a clock for the usb full speed controller ? one 80 to 240 mhz programmable pll (plla), provides the clock, mck to the processor and peripherals. the plla input frequency is from 3 mhz to 32 mhz. figure 10 - 2. clock generator block diagram p o w er m anageme n t c on tr oller xin x out m ain clock m ainck c on tr ol s ta tus pll and divider a plla clock pll a ck 12m m ain oscill a t or pll and divider b on chip 32k r c osc sl o w clock sl ck xin32 x out32 sl o w clock oscill a t or clock g ene r a t or x t alsel pllb clock pllbck on chip 12/8/4 m h z r c osc m ainsel www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 49 10.6 power m anagement controller the power management controller provides all the clock signals to the system. it provides: ? the processor clock, hclk ? the free running processor clock, fclk ? the cortex systick external clock ? the master clock, mck, in particular to the matrix and the memory interfaces ? the usb clock, udpck ? independent peripheral clocks, typically at the frequency of mck ? three programmable clock outputs: pck0, pck1 and pck2 the supply controller selects bet we en the 32 khz rc oscillator and the crystal oscillator. the unused oscillator is disabled automatically so that power consumption is optimized. by default, at startup the chip runs out of the master clock using the fast rc oscillator running at 4 mhz. th e user can trim the 8 and 12 mhz rc oscillator frequency by software. figure 10 - 3. power management controller block diagram mck pe r iph_clk[..] in t sl ck m ainck pll a ck p r escaler /1,/2,/4,...,/64 hck p r oc essor clock c on tr oller sleep m ode m as t er clock c on tr oller p er iphe r als clock c on tr oller on/off usb clock c on tr oller sl ck m ainck pll a ck p r escaler /1,/2,/4,...,/64 p r og r ammable clock c on tr oller pllbck pck[..] pllbck pllbck udpck on/off on/off fclk s y st t ick divider /8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 50 the systick calibration value is fixed at 12500, which allows the generation of a time base of 1 ms with systick clock at 12.5 mhz (max hclk/8 = 100 mhz/8 = 12500, so stcalib = 0x30d4). 10.7 watchdog timer ? 16- bit key - protected only - once programmable counter ? windowed, prevents the processor to be in a deadlock on the watchdog access 10.8 systick timer ? 24- bit down counter ? self - reload capability ? flexible system timer 10.9 real time timer ? real - time timer, allowing backup of time with different accuracies ? 32- bit free - running backup counter ? integrates a 16 - bit programmable prescaler running on slow clock ? alarm register capable to generate a wake - up of the system through the shut down controller 10.10 real time clock ? low power consumption ? full asynchronous design ? two hundred year gregorian and persian calendar ? programmable periodic interrupt ? trimmable 32.7682 khz crystal oscillator clock source ? alarm and update parallel load ? control of alarm and update time/calendar data in ? waveform output capability on gpio pins in low power modes 10.11 general - purpose backup registers ? eight 32 - bit backup general - purpose registers 10.12 nested vectored interrupt controlle r ? thirty maskable external interrupts ? sixteen priority levels ? processor state automatically saved on interrupt entry, and restored on ? dynamic reprioritizing of interrupts ? priority grouping. ? selection of pre - empting interrupt levels and non pre - empting interrupt levels. ? support for tail - chaining and late arrival of interrupts. ? back - to - back interrupt processing without the overhead of state saving and restoration between interrupts. ? processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 51 10.13 chip identification ? chip identifier (chipid) registers permit recognition of the device and its revision. table 10 - 1. sam4sp32a chip ids register chip name flash size (kbytes) ram size (kbytes) pin count chipid_cidr chipid_exid samsp32a 212 1 12 x2 a _ee - jtag id b3_23f 10.14 uart ? two - pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? support for two pdc channels with connection to receiver and transmitter 10.15 pio controllers ? 3 pio co ntrollers, pioa, piob and pioc controlling a maximum of 37 i/o lines ? each pio controller controls up to 22 programmable i/o lines ? fully programmable through set/clear registers table 10 - 2. pio available on sam4sp32a version pins pioa 22 piob 12 pioc 3 ? multiplexing of four peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change interrupt ? programmable glitch filter ? programmable debouncing filter ? multi - drive option enables driving in open drain ? programmable pull - up on each i/o line ? pin data status register, supplies visibility of the level on the pin at any time ? additional interrupt modes on a programmable event: rising edge, falling edge, low l evel or high level ? lock of the configuration by the connected peripheral ? synchronous output, provides set and clear of several i/o lines in a single write ? write protect registers ? programmable schmitt trigger inputs ? parallel capture mode www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 52 ? can be used to interface a cmos digital image sensor , etc .... ? one clock, 8 - bit parallel data and two data enable on i/o lines ? data can be sampled one time out of two (for chrominance sampling only) ? supports connection of one peripheral dma controller channel (pdc) whi ch offers buffer reception without processor intervention www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 53 10.16 peripheral identifiers table 10 - 3 defines the peripheral identifiers of the sam4sp32a . a peripheral identifier is required for the control of the peripheral interrupt with the nested vectored interrupt controller and control of the peripheral clock with the power management controller. table 10 - 3. peripherical identifiers instance id instance name nvic interrupt pmc clock control instance description supc x supply controller 1 rstc x reset controller 2 rtc x real time clock 3 rtt x real time timer wdt x watchdog timer pmc x power management controller efc x enhanced embedded flash controller efc1 x enhanced embedded flash controller 1 uart x x uart uart1 x x uart 1 1 smc x x static memory controller 11 pioa x x parallel i/o controller a 12 piob x x parallel i/o controller b 13 pioc x x parallel i/o controller c 1 usart x x usart 1 usart1 x x usart 1 1 - - - reserved 1 - - - reserved 1 - x x reserved 1 twi x x two wire interface 2 twi1 x x two wire interface 1 21 - - - reserved 22 ssc x x synchronous serial controller 23 tc x x timer/counter 2 tc1 x x timer/counter 1 2 - - - reserved 2 - - - reserved 2 - - - reserved 2 - - - reserved 2 - reserved 3 - reserved 31 pwm x x pulse width modulation 32 crccu x x crc calculation unit 33 acc x x analog comparator 3 udp x x usb device port www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 54 10.17 peripheral signal multiplexing on i/o lines the sam4sp32a features 3 pio controllers (pioa, piob and pioc), that multiplex the i/o lines of the peripheral set. the sam4sp32a control s up t o 2 2 lines. each line can be assigned to one of three peripheral functions: a, b or c. the mu ltiplexing tables in the follow ing paragraphs define how the i/o lines of the peripherals a, b and c are multiplexed on the pio controllers. the column ?comments? has been inserted in this table for the user?s own comments; it m ay be used to track how pins are defined in an application. note that some peripheral functions which are output only, might be duplicated within the tables. 10.17.1 pio controller a multiplexing table 10 - 4. multiplexing on pio controller a (pioa) i/o line peripherical a pe ripherical b peripherical c extra function system function comment pa0 pwmh0 tioa0 a17 wkup0 pa1 pwmh1 tiob0 a18 wkup1 pa2 pwmh2 sck0 datrg wkup2 pa3 twd0 npcs3 pa4 twck0 tclk0 wkup3 pa5 rxd0 npcs3 wkup4 pa6 txd0 pck0 pa7 rts0 pwmh3 xin32 pa8 cts0 adtrg wkup5 xout32 pa9 urxd0 npcs1 pwmfi0 wkup6 pa10 utxd0 npcs2 pa15 tf tioa1 pwml3 wkup14/piodcen1 pa16 tk tiob1 pwml2 wkup15/piodcen2 pa17 td pck1 pwmh3 ac 0 pa18 rd pck2 a14 ac 1 pa19 rk pwml0 a15 ac 2/wkup9 pa20 rf pwml1 a16 ac 3/wkup10 pa21 rxd1 pck1 pa22 txd1 npcs3 ncs2 pa23 sck1 pwmh0 a19 piodcclk pa24 rts1 pwmh1 a20 piodc0 pa25 cts1 pwmh2 a23 piodc1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 55 10.17.2 pio controller b multiplexing table 10 - 5. multiple xing on pio controller b (piob ) i/o line peripherical a peripherical b peripherical c extra function system function comment pb0 pwmh0 ac 4/rtcout0 pb1 pwmh1 ac 5/rtcout1 pb2 urxd1 npcs2 ac 6/wkup12 pb3 utxd1 pck2 ac 7 pb4 twd1 pwmh2 tdi pb5 twck1 pwml0 wkup13 tdo/traceswo pb6 tms/swdio pb7 tck/swclk pb8 xou t pb9 xin pb10 dmm pb11 dpp pb12 pwml1 erase 10.17.3 pio controller c multiplexing table 10 - 6. multiplexing on pio controller c (pioc) i/o line peripherical a peripherical b peripherical c extra function system function comment pc0 d0 pwml0 pc5 d5 pc26 a8 tioa4 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 56 11. embedded peripherals overview 11.1 two wire interface (twi) ? master, multi - master and slave mode operation ? compatibility with atmel two - wire interface, serial memory and i 2 c compatible devices ? one, two or three bytes for slave address ? sequential read/write operations ? bit rate: up to 400 kbit/s ? general call supported in slave mode ? connecting to pdc channel capabilities optimizes data transfers in master mode only ? one ch annel for the receiver, one channel for the transmitter ? next buffer support 11.2 universal asynchronous receiver transceiver (uart) ? two - pin uart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parit y generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? support for two pdc channels with connection to receiver and transmitter 11.3 usart ? programmable baud rate generator ? 5 - to 9 - bit full - d uplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb - or lsb - first ? optiona l break generation and detection ? by 8 or by - 16 over - sampling receiver frequency ? hardware handshaking rts - cts ? receiver time - out and transmitter timeguard ? optional multi - drop mode with address generation and detection ? optional manchester encoding ? full modem line support on usart1 (dcd - dsr - dtr - ri) ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? spi mode ? master or slave ? serial clo ck programmable phase and polarity ? spi serial clock (sck) frequency up to mck/4 ? irda modulation and demodulation www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 57 ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo 11.4 synchronous serial controller (ssc) ? provides serial synchronous communication links used in audio and telecom applications (with codecs in master or slave modes, i 2 s, tdm buses, magnetic card reader) ? contains an independent receiver and transmitter and a common clock divider ? offers configurable frame sync and data length ? receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal, a clock signal and a frame synchr onization signal 11.5 timer counter (tc) ? two 16 - bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities ? each channel is user - configurable and contains: ? one external clock input ? five internal clock inputs ? two multi - purpose input/output signals ? two global registers that act on all three tc channels ? quadrature decoder ? advanced line filtering ? position / re volution / speed ? 2 - bit gray up/down counter for stepper motor 11.6 pulse width modulation controller (pwm) ? one four - channel 16 - bit pwm controller, 16 - bit counter per channel ? common clock generator, providing thirteen different clocks ? a modulo n counter provi ding eleven clocks ? two independent linear dividers working on modulo n counter outputs ? high frequency asynchronous clocking mode ? independent channel programming ? independent enable disable commands ? independent clock selection ? independent period and du ty cycle, with double buffering ? programmable selection of the output waveform polarity www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 58 ? programmable center or left aligned output waveform ? independent output override for each channel ? independent complementary outputs with 12 - bit dead time generator for each channel ? independent enable disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? synchronous channel mode ? synchronous channels s hare the same counter ? mode to update the synchronous channels registers after a programmable number of periods ? connection to one pdc channel ? provides buffer transfer without processor intervention, to update duty cycle of synchronous channels ? one progra mmable fault input providing an asynchronous protection of outputs ? stepper motor control (2 channels) 11.7 usb device port (udp) ? usb v2.0 full - speed compliant,12 mbits per second. ? embedded usb v2.0 full - speed transceiver ? embedded 2688 - byte dual - port ram for endpoints ? eight endpoints ? endpoint 0: 64bytes ? endpoint 1 and 2: 64 bytes ping - pong ? endpoint 3: 64 bytes ? endpoint 4 and 5: 512 bytes ping - pong ? endpoint 6 and 7: 64 bytes ping - pong ? ping - pong mode (two memory banks) for isochronous and bulk endpoints ? suspend/resume logic ? integrated pull - up on ddp ? pull - down resistor on ddm and ddp when disabled 11.8 analog comparator ? one analog comparator ? high speed option vs. low - power option ? $ [ [ q v d f w l y h f x u u h q w f r q v x p s w l r q s u r s d j d w l r q g h o d \ ? $ /xx ns active current consumption/propagation delay ? selectable input hysteresis ? 0, 15 mv, 30mv (typ) ? minus input selection: ? temperature sensor ? advref ? plus input selection: ? all analog inputs ? output selection: ? internal signal www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 59 ? external pin ? selectabl e inverter ? window function ? interrupt on: ? rising edge, falling edge, toggle ? signal above/below window, signal inside/outside window 11.9 cyclic redundancy check calculation unit (crccu) ? 32- bit cyclic redundancy check automatic calculation ? crc calculation bet ween two addresses of the memory 11.10 plc brigde ? six i/o lines to connect to prime plc transceiver for external configurations www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 60 12. prime plc t ransceiver the sam4sp32a mcu embeds a certified prime power line communication transceiver with a featured class d power amplifier and a set of hardware accelerators blocks to execute the heavy tasks of the prime protocol without the interruption of the cortex - m4 cpu. the prime plc transceiver peripheral integrates: ? power line carrier modem for 50 and 60 hz mains ? 97- carr ier ofdm prime compliant ? baud rate selectable: 21400 to 128600 bps ? differential bpsk, qpsk, 8 - psk modulations ? automatic gain control and signal amplitude tracking ? embedded on - chip dmas ? media access control ? viterbi decoding and crc prime compliant ? 128 - bit a es encryption ? channel sensing and collision pre - detection www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 61 12.1 sam4sp32a prime phy layer 12.1.1 sam4sp32a phy layer the physical layer of sam4sp32a consists of a hardware implementation of the prime physical layer entity, which is an orthogonal frequency division mu ltiplexing (ofdm) system in the cenelec a - band. this phy layer transmits and receives mpdus (mac protocol data unit) between neighbor nodes. from the transmi ssion point of view , the phy layer receives its inputs from the mac (medium access control) layer , via dma . at the end of transmission branch, data is output to the physical channel. on the reception side, the phy layer receives its inputs from the physical channel, and at the end of reception branch, the data flows to the mac layer, via dma. a phy lay er block diagram is shown below: figure 12 - 1. sam4sp32a phy layer block diagram the diagram can be divided in four sub - blocks: transmission branch, emission branch, analog front end control and carrier detection. aes block crc aes block crc scrambler interleaver fft scrambler interleaver ifft converter sam 4 sp 32a phy layer tx rx vsense psense agc 0 agc 1 afe _ himp afe _ txrx convolutional encoder test mode sub - carrier modulator cyclic prefix converter / pad carrier detection analog front - end control power supply sensing gain control line impedance control txrx control from dma mac layer to c pre - fft syncro sub - carrier demodulator convolutional decoder mac layer to dma www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 62 12.1.1.2 transmission and reception branches phy layer takes data to be sent from dedicated dma channel (phy_tx). 128 - bit aes encryption is done ?on the fly?, and the clyclic redundancy check ( crc) fields are hardware - generated in real time. these crcs are properly appended to the transmission data. the rest of the chain is hardware - wired, and performs automatically all the tasks needed to send data according to prime specifications. in figure 12 - 2 , the block diagram of the transmission brach is shown . figure 12 - 2. transmission branch the output is differentially modulated using a bpsk/dqpsk/d8psk scheme. after modulation, ifft (inverse fourier tr ansform) block and cyclic prefix block allows to implement an ofdm scheme. a converter and a power amplifier driver is the last block in the transmission branch. this block is responsible for adjusting the signal to reach the best transmission efficiency, thus reducing consumption and power dissipation. test mode: when selected, test mode injects data directly to sub - carrier modulation block. when in test mode, data can be injected continuously to the line using only a set of selected frequencies, in order to test channel behavior. the reception branch performs automatically all the tasks needed to process received data. phy layer delivers data to mac layer through the dedicated dma channel (phy_rx). figure 12 - 3. reception branch 12.1.1.3 carrier detection looking for an easy detection of incoming messages, prime specification defines a chirp signal located at the beginning of the prime frames devised to ease synchronization in the receptor. by means of detection techniques, the receiver can know accurately when the chirp has been completely received and then the correct instant when the frame begins. before starting a transmission, it is also necessary to use carrier detection in order to check if another device is already emitting, thus avoiding collisions. if any device is e mitting, the carrier detection triggers a microcontroller interruption and sets an internal flag, thus the transmission will be stopped. the main drawback of this process is that chirp signal length (2.4 milliseconds) is not short enough to guarantee very low collision ratio. aes block crc sub - carrier modulator convolutional encoder scrambler interleaver test mode ifft cyclic prefix converter / pad from dma tx rx to dma aes block crc convolutional decoder scrambler sub - carrier demodulator interleaver fft pre - fft syncro converter www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 63 to improve this drawback, the ofdm plc modem implements two different algorithms to detect the carrier as soon as possible, aiming to reduce collisions and improving the medium access behavior. by these early detection techniques, the system achieves low collision ratio, and the communication throughput increases significantly. 12.1.1.4 analog front end control the phy layer controls the analog front end by means of four sub - blocks: ? power supply sensing ? gain control ? line impedance control ? txrx c ontrol 12.1.1.5 power supply sensing : vsense and psense the power supply is continuously monitored to avoid power supply failures that could damage the supply device. this block senses the power channel using two different inputs: ? vsense: vsense detects whether voltage falls below 3.3v during a number of cycles while a message is being transmitted. this measurement is done after a transitory guard time (ttrans in figure below). if a voltage failure occurs, the transmission is shut down and sending messages again will be not possible if an internal flag (vfailure) is not previously cleared. figure 12 - 4. transitory guard time in message transmission ? psense: psense measures the power source current consumption, shutting down the transmission if the consumption exceeds a defined threshold (stored in maxpot phy layer registers, see 12.1.5.34 ) . this measurement is done after a transitory guard time. as the current measurement varies over time, an averaging is done taking into account an average parameter (alpha), a configurable number of cycles (numcycles, see 12.1.5.35 ) and a configurable length of each cycle (a_nummilis, see 12.1.5.36 ). ttrans (no measuring voltage failures ) message transmision measuring possible voltage failures www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 64 if a power failure occurs, the transmission is shut down and sending messages again will be not possible if an internal flag (pfailure, see 12.1.5.22 ) is not previously cleared. the system considers that a power failure has occurs when the value read from mean registers ( see 12.1.5.30 ) is above the user - definable value stored in maxpot registers. figure 12 - 5. psense parameters psense and vsense configurations parameters are automatically set by the phy layer . see related peripheral registers for more information about psense and vsense. 12.1.1.6 gain control this block implements two automatic gain control outputs to adjust the received signal level to a suitable range. both of them are set to ?1? when the received sign al is above two system thresholds in order to activate external attenuators placed in the external analog front end. the value of these outputs is set during the be ginning of a received message and is hold until the end of the message. agc 0 and agc1 follow different algorithms, thus u sing both of them ensures a more accurate gain control. see agc_config register in for information about agc configuration. 12.1.1.7 line impedance control this block modifies the configuration of the analog front end by means of afe - himp output. when working with a suitable external configuration, the system can change the filter conditions in order to adjust its behavior to the line impedance values. see last sam4sp32a reference design for further information about line impedance topologies. trans_psense message transmision num_milis num_milis num_milis num_milis num_milis num_cycles new psense cycles value new psense cycles value new psense cycles value new psense cycles value new psense cycles value new mean value new mean value new mean value www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 65 12.1.1.8 txrx control this block modifies the configuration of the analog front end by means of afe - txrx output. thus is possible to change filter conditions between transmission/reception. see reference design for further information about txrx contr ol. 12.1.2 phy parameters as described below, the phy layer is specified by certain main parameters, which are fixed for each specific constellation/coding combination. these parameters have to be identical in a network in order to achieve compatibility. table 12 - 1. prime ph y main parameters prime phy parameter value base band clock (hz) 250000 subcarrier spacing (hz) 488,28125 number of data subcarriers 84 (header) , 96 (payload) number of pilot subcarriers 13 (header) , 1 (payload) fft interval (samples) 512 fft interval ( s) 2048 cyclic prefix (samples) 48 cyclic prefix ( s) 192 symbol interval (samples) 560 symbol interval ( s) 2240 preamble period ( s) 2048 table 12 - 2 shows the phy data rate during payload transmission, and maximum msdu length for various modulation and coding combinations table 12 - 2. phy parameters depending on the modulation dbpsk dqpsk d8psk convolutional code (1/2) on off on off on off information bits per subcarrier 0,5 1 1 2 1,5 3 information bits per ofdm symbol 48 96 96 192 144 288 raw data rate (kbps approx) 21,4 42,9 42,9 85,7 64,3 128,6 max msdu length with 63 symbols (bits) 3016 6048 6040 12096 9064 18144 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 66 table 12 - 3 shows the modulation and coding scheme and the size of the header portion of the phy frame table 12 - 3. header parameters dbpsk convolutional code (1/2) on information bits per subcarrier 0,5 information bits per ofdm symbol 42 all the parameters of the physical layer such as the base band clock, subcarrier spacing, number of subcarriers...; are defined in prime specification, and have to be identical in a network in order to achieve compatibility . 12.1.3 phy protocal data unit (ppdu) format figure 12 - 6 shows how ofdm symbols are transmitted in a ppdu (physical layer protocol data unit). the preamble is used at the beginning of every ppdu for synchronization purposes. figure 12 - 6. phy layer transmitter block diagram phy layer adaptively modifies attenuation values applied to the whole signal. also, additional attenuations are applied to the chirp section of the signal (preamble) and to the rest of the signal itself (header+payload), to smoothly adapt amplitude values and transitions. figure 12 - 7. ppdu ofdm symbols and duration 12.1.4 phy service specification there is an interface specified in prime for the phy layer, with several primitives relative to both data and control planes. phy layer has a single 20 - bit free - running clock measured in 10 s steps . time measured by this clock is the one to be used in some phy primitives to indicate a specific instant in time. sam4sp32a includes a hardware implementation of this clock, which consists of a 20 - bit register. this register is read - only and it can be accessed as a 32 - bit variable by the add8051c3a microcontroller. crc convolutional encoder scrambler interleaver sub-carrier modulator ifft cyclix prefix preamble header payload 2 ,048 ms 4 ,48 ms / 2 ofdm symbols 2 ,24 * m ms / m ofdm symbols header : ? dbpsk ? fec : ? always on payload : ? dbpsk , dqpsk , d 8 psk ? fec : ? on / off www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 67 figure 12 - 8. header and payload structure prime specifies a complete set of primitives to manage the phy layer, and the phy - sap (phy service access point) from mac layer. atmel prime stack integrates all this functions, making them transparent to the final user and simplifying the management. protocol len pad _ len mac _h 4 bits 6 bits 6 bits 54 bits crc_ ctrl 8 bits flushing _h 6 bits phy header , 84 bits pad flushing _d phy payload msdu 8 bits 8 xm bits 8 xp bits www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 68 12.1.5 phy layer registers relative addresses in the plc modem intenrnal memory map given. 12.1.5.1 phy_sfr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 phy_sfr bch_err cd umd -- -- txrx -- int_phy name: phy_sfr address: 0xfe2a access: read/write reset: 0x87 ? - - : reserved bit ? bch_err: busy channel error flag . this bit is set to ?0? by hardware to indicate the presence of an ofdm signal at the transmission instant. otherwise, this field value is ?1?. this bit is used for returning a result of ?busy channel? in the phy_data.confirm primitive (see prime specification). ? cd: carr ier detect bit. this bit is set to ?1? by hardware when an ofdm signal is detected, and it is active during the whole reception. this bit is used in channel access (csma - ca algorithm) for performing channel - sensing. ? umd : uns upported modulation scheme flag . this flag is set to ?1? by hardware every time a header with correct crc is received, but the protocol field in this header indicates a modulation scheme not supported by the system. ? txrx: transmission order . when data to transmit is ready at addr_phy_in i_tx in data memory, the time value is set at tx_time register and then the emission level is specified at attenuation register, then txrx bit has to be set to '0' in order to init transmission. if this bit is read, only returns '0' when physical transmis sion has started. otherwise, it returns '1'. the transmission will begin when timer_beacon_ref is equal to tx_time. ? int_phy : physical layer interruption this bit is internally connected to the external microcontroller interrupt /ext_int. it is low - level active. it is set to '0' by physical layer and is cleared by writing '1' in the bit phy_sfr(0). www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 69 12.1.5.2 sys_config register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 sys_config -- conv_pd phy_pd phy_err_en phy_err phy_rst name: sys_config address: 0xfe2c access: read/write reset: 0x04 ? --: reserved bits ? conv_pd : converter power down the sam4sp32a m icrocontroller can activate internal converter power down mode by setting this bit. when internal converter is in power down mode, the system is unable to receive. this bit is high - level active. ? phy_pd : phy power down this bit shuts down physical layer clock. when in phy power down mode, all the system blocks involved in communication remain inactive. thus, the system will be unable to transmit or receive. the next sequence mu st be respected to ensure proper power down : setting phy power down mode 1 - set physical layer reset (sys_config(0)), phy_rst=?1? 2 - set conv_pd and phy_pd fields exiting phy power down mode 1 - clear conv _pd and phy_pd fields 2 - cle ar physical layer reset (sys_config(0)), phy_rst=?0? this bit is high - level active . ? phy_err_en : physical layer watchdog enable this bit enables or disables physical layer watchdog. physical layer watchdog is enabled by default . this bit is high - level active . ? phy_en : physical layer error flag this flag indicates if a physical layer error has occurred. physical layer watchdog has a 200milliseconds sampling period. when physical layer detects an error, it activates the physical layer interrupt and this flag is set. to restore situation, microcontroller must reset physical layer by means of phy_rst bit (sys_config(0)). ? phy_rst : physical layer reset this bit resets the physical layer. to perform a physical layer reset cycle, microcontroller must set this bit to ?1 ? and then must clear it to ?0?. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 70 12.1.5.3 phy_config register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 phy_config -- cinr_mode pad_len_ac aes_en cd_mod1_en cd_mod2_det mac_en name: phy_config address: 0xfe68 access: read/write reset: 0x1f ? --: reserved bits ? cinr_mode : carrier to interference + noise ratio mode this bit enables /disables cinr mode when set to ?1? . ? ?0?: cinr mode disabled. ? ?1?: cinr mode enabled. ? pad_len_ac : this field allows the system to work with two different representations of the phy header pad_len field ( pad_len represented before coding or pad_len represented after coding). ? ? 0 ?: pad_len field in phy header is represented before coding. this is the suitable value to fulfill prime specification. ? ? 1 ?: pad_len field in phy header is represented after coding. ? aes_en : this field enables/disables ?on the fly? aes encryption and decryption by hardware. ? ? 0 ?: ?on the fly? aes encryption/decryption disabled. ? ?1?: ?on the fly? aes encryption/decryption enabled. ? cd_mod1_en : this field enables/disables carrier detectio n mode 1. ? ? 0 ?: carrier detection mode 1 disabled. ? ?1?: carrier detection mode 1 enabled. ? cd_mod2_det: this field enables/disables carrier detection mode 2. ? ? 0 ?: carrier detection mode 2 disabled. ? ?1?: carrier detection mode 2 enabled. ? mac_en : this field enables/disables crc processing by hardware. ? ? 0 ?: crc processing disabled. ? ? 1 ?: crc processing enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 71 12.1.5.4 attenuation register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 attenuation attenuation(7:0) name: attenuation address: 0xfe24 access: read/write reset: 0xff ? attenuation : global attenuation for the transmitted signal (chirp+signal). the 16 - bit signal level is multiplied by this 8 - bit value and the result is truncated to 16 bits. attenuation value = 0xff ? the transmitted signal amplitude is not attenuated. atte nuation value = 0x00 ? the transmitted signal amplitude is nullified. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 72 12.1.5.5 att_chirp register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 att_chirp att _chirp (7:0) name: att_chirp address: 0xfe9b access: read/write reset: 0xff ? att_chirp : this register stores the attenuation value for the chirp. the 16 - bit chirp data is multiplied with this 8 - bit value and the 24 - bit result is truncated to 16 bits. attenuation value = 0xff ? the chirp amplitude is not attenuated attenuation value = 0x00 ? the chirp amplitude is nullified www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 73 12.1.5.6 att_signal register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 att_signal att _signal (7:0) name: att_signal address: 0xfe9c access: read/write reset: 0xff ? att_signal : this register stores the attenuation value for the signal without the chirp section. the 16 - bit chirp data is multiplied with this 8 - bit value and the 24 - bit result is truncated to 16 bits. attenuation value = 0xff ? the signal amplitude is not attenuated attenuation value = 0x00 ? the signal amplitude is nullified www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 74 12.1.5.7 tx_time registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 tx_time tx_time(19:12) @0xfe26 tx_time(11:4) @0xfe27 tx_time(3:0) ?0000? @0xfe28 ?00000000? @0xfe29 name: tx_time address: 0xfe26 ? 0xfe29 access: read/write reset: 0x00, ?, 0x00; ? tx_time: this 20 - bit value sets the time instant when the mpdu (mac protocol data unit) has to be transmitted. the time is expressed in 10 s steps. when writing a new value to tx_time register, a specific writing order must be taken, always from the most significan t byte (tx_time(19:12) at address 0xfe26) to the least significant byte (tx_time(3:0) at address 0xfe28), and it is required to write the 3 bytes to avoid wrong time comparisons in transmission. the 20 - bit tx_time value is managed by the microcontroller as a 4 - byte variable. the tx_time value is aligned to the 20 most significant bits, being the 12 least significant bits padded with zeros. this register is used by the physical layer for being in accordance with prime specifications about transmission time ( see prime spec.) note: txrx bit (phy_sfr(2)) has to be cleared to ?0? in order to init transmission. once this bit has been cleared, the transmission will start when timer_beacon_ref value is equal to tx_time. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 75 12.1.5.8 timer_frame registers name bit 7 bit 6 bi t 5 bit 4 bit 3 bit 2 bit 1 b it 0 timer_frame timer_frame(19:12) @0xfe2d timer_frame(11:4) @0xfe2e timer_frame(3:0) ?0000? @0xfe2f ?00000000? @0xfe30 name: timer_frame address: 0xfe2d ? 0xfe30 access: read only reset: 0x00, ?, 0x00; ? timer frame : time of receipt of the preamble associated with the psdu (phy service data unit). it is expressed in 10 s steps and is taken from the physical layer timer timer_beacon_ref. it is set by hardware and is a read - only register. this register is used by the physical layer for being in accordance with prime specification about reception time (see prime specification). the 20 - bit timer_frame value is managed by the microcontroller as a 4 - byte variable. the timer_frame value is alig ned to the 20 most significant bits, being the 12 least significant bits padded with zeros. this simplifies arithmetic calculations with time values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 76 12.1.5.9 timer_beacon_ref registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 timer_beacon_ref timer_beacon_ref(19:12) @0xfe47 timer_beacon_ref (11:4) @0xfe48 timer_beacon_ref (3:0) ?0000? @0xfe49 ?00000000? @0xfe4a name: timer_beacon_ref address: 0xfe47 ? 0xfe4a access: read only reset: 0x00, ?, 0x00; ? t imer _ beacon_ref : timer for the physical layer, which consists of a single 20 - bit free - running clock measured in 10 s steps. it indefinitely increases a unit each 10 microseconds from 0 to 1048575, overflowing back to 0. it is set by hardware and is a read - only register. this register is used by the physical layer for being in accordance with prime specification. it is reserved 32 - bit in data memory to be able to declare as 32 - bit variable. the 20 - bit register msb is aligned to the 32 - bit variable msb, in order to simplify arithmetic calculations with time values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 77 12.1.5.10 rx_level registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 rx_level rx_level(15:8) @0xfe31 rx_level(7:0) @0xfe32 name: table_element_init address: 0xfe31 ? 0xfe32 access: read only reset: 0x00; 0x00 ? rx_level : these registers store the autocorrelation level of the chirp signal. when the reception process has started, th e s e registers are set by hardware. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 78 12.1.5.11 rssi_min register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 rssi_min rssi_min(7:0) name: rssi_min address: 0xfe33 access: read only reset: 0xff ? rssi_min : received signal strength indication min this register stores the minimum rssi value measured in the last message received. the measurement is done at symbol level. the value is stored in ?db steps www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 79 12.1.5.12 rssi_avg register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 rssi_avg rssi_avg(7:0) name: rssi_avg address: 0xfe34 access: read only reset: 0x00 ? rssi_avg : received signal strength indication average this register stores the average rssi value measured in the last message received. the measurement is done at symbol level. the value is stored in ?db steps www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 80 12.1.5.13 rssi_max register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 rssi_max rssi_max(7:0) name: rssi_max address: 0xfe35 access: read only reset: 0x00 ? rssi_max : received signal strength indication max this register stores the maximum rssi value measured in the last message received. the measurement is done at symbol level. the value is stored in ?db steps www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 81 12.1.5.14 cinr_min register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 cinr_min cinr_min(7:0) name: cinr_min address: 0xfe38 access: read only reset: 0xff ? cinr_min : carrier to interference + noise ratio min this register stores the minimum cinr value measured in the last message received. in order to calculate cinr properly, the algorithm takes beacon - type messages as a reference, since this message type allows knowing its content beforehand. the system uses a table that must be loaded with the beacon data to be received, so cinr mode must be activated (see phy_config register) and the same procedure used to send beacons must be followed. as cinr mode is activated, physical layer will load the message in the table instead of sending it (table load time is in the order of microseconds, and is much shorter than the one used to send the message). once the table is loaded, cinr must be disabled, and next messages cinr will be calculated taken the beacon loaded in the table as reference . the measurement is done at symbol level. the value is stored in ?db steps. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 82 12.1.5.15 cinr_avg register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 cinr_avg cinr_avg(7:0) name: cinr_avg address: 0xfe39 access: read only reset: 0x00 ? cinr_avg : carrier to interference + noise ratio average this register stores the average cinr measured in the last message received. in order to calculate cinr properly, the algorithm takes beacon - type messages as a reference, since this message type allows knowing its content beforehand. the system uses a table that must be loaded with the beacon data to be received, so cinr mode must be activated (see phy_config register) an d the same procedure used to send beacons must be followed. as cinr mode is activated, physical layer will load the message in the table instead of sending it (table load time is in the order of microseconds, and is much shorter than the one used to send t he message). once the table is loaded, cinr must be disabled, and next messages cinr will be calculated taken the beacon loaded in the table as reference the measurement is done at symbol level. the value is stored in ?db steps. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 83 12.1.5.16 cinr_max register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 cinr_max cinr_max(7:0) name: cinr_max address: 0xfe3a access: read only reset: 0x00 ? cinr_max : carrier to interference + noise ratio max this register stores the maximum cinr value measured in the last message received. in order to calculate cinr properly, the algorithm takes beacon - type messages as a reference, since this message type allows knowing its content beforehand. the system uses a table that must be loaded with the beacon data to be received, so cinr mode must be activated (see phy_config register) and the same procedure used to send beacons must be followed. as cinr mode is activated, physical layer will load the message in the table instead of sending it (table load time is in the order of microseconds, and is much shorte r than the one used to send the message). once the table is loaded, cinr must be disabled, and next messages cinr will be calculated taken the beacon loaded in the table as reference the measurement is done at symbol level. the value is stored in ?db steps . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 84 12.1.5.17 evm_header registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 evm_header evm_header(15:8) @0xfe3b evm_header (7:0) @0xfe3c name: evm_header address: 0xfe3b ? 0xfe3c access: read only reset: 0x00; 0x00 ? evm_header : header error vector magnitude - these registers store in a 16 - bit value the maximum error vector magnitude measured in the reception of a message header. the 7 msb (evm_header(15:9)) represent the integer part in %, being the evm_header(8:0) bits the fractional part if more precision were required. this register is used by the physical layer for being in accordance with prime specification. it is reserved 32 - bit in data memory to be able to declare as 32 - bit variable. the 20 - bit register msb is aligned to the 32 - bit variable msb, in order to simplify ar ithmetic calculations with time values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 85 12.1.5.18 evm_payload registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 evm_payload evm_payload(15:8) @0xfe3d evm_payload(7:0) @0xfe3e name: evm_payload address: 0xfe3d ? 0xfe3e access: read only reset: 0x00; 0x00 ? evm_payload : payload error vector magnitude - these registers store in a 16 - bit value the maximum error vector magnitude measured in the reception of a message payload . the 7 msb (evm_ payload (15:9)) represent the integer part in %, being the evm_ payload (8:0) bits the fractional part if more precision were required. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 86 12.1.5.19 evm_header_acum registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 evm_header_acum evm_header_acum(19:12) @0xfe3f evm_header_acum (11:4) @0xfe40 evm_header_acum (3:0) ?0000? @0xfe41 ?00000000? @0xfe42 name: evm_header_acum address: 0xfe3f ? 0xfe42 access: read only reset: 0x00, ?, 0x00; ? evm_header_acum : header total error vector magnitude accumulator when receiving an ofdm symbol, the summation of all its individual carriers evms is calculated in order to further calculate the average evm value. these registers store the maximum summation between the two ofdm symbols received in a message header. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 87 12.1.5.20 evm_payload_acum registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 evm_payload_acum evm_payload_acum(19:12) @0xfe43 evm_payload_acum(11:4) @0xfe44 evm_payload_acum(3:0) ?0000? @0xfe45 ?00000000? @0xfe46 name: evm_payload_acum address: 0xfe43 ? 0xfe46 access: read only reset: 0x00, ?, 0x00; ? evm_payload_acum : payload total error vector magnitude accumulator when receiving an ofdm symbol, the summation of all its individual carriers evms is calculated in order to further calculate the average evm value. these registers store the maximum summation between all the ofdm symbols received in a message payload. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 88 12.1.5.21 rms_calc register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 rms_calc rms_calc(7:0) name: rms_calc address: 0xfe58 access: read only reset: 0x00 ? rms_calc : this register stores an 8 - bit value which magnitude is proportional to the emitted signal amplitude. by measuring the amplitude of the emitted signal, the hardware can estimate the power line input impedance. thus hardware can adjust emission configuration appropriately. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 89 12.1.5.22 vsense_config register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 vsense_config -- pfailure psense_soft vfailure vsense_en name: vsense_config address: 0xfe59 access: read only reset: 0x00 ? pfailure : power failure flag this flag is set to 1 when a power failure occurs. the transmission is stopped and a new transmission is not possible if this flag is not cleared previously. when a power failure occurs, a consideration about decreasing voltage amplitude in the source should be taken. this flag must be cleared by software. ? psense_soft: current measurement is done every time a transmission takes place. with psense_soft the system can force a continuous current measurement, including both idle and transmission states. ? ? 0 ?: current consumption is measured every time a transmission begins (after a guard time defined by trans_psen se). nummilis, numcycles and trans_psense values must be taken into account to accurate psense measurements. this is the default mode and it is the expected one when sam4sp32a is working. ? ?1?: current consumption is measured both in idle and transmission s tates. this mode is useful for design purposes, in order to find suitable values for the current threshold (maxpot registers) depending on the external net requirements. ? vfailure: voltage failure flag this flag is set to 1 when a voltage failure occurs. th e transmission is stopped and a new transmission is not possible if this flag is not cleared previously. when a voltage failure occurs, a consideration about decreasing voltage amplitude in the source should be taken. this flag must be cleared by software. ? vsense_en: vsense enable this bit enables vsense. ? ? 0 ?: vsense disabled (default). ? ? 1 ?: vsense enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 90 12.1.5.23 num_fails register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 num_fails num_fails(7:0) name: num_fails address: 0xfe5a access: read/write reset: 0x02 ? num_fails : this register stores the number of 50 ns cycles (clk=20mhz) during which a voltage failure must be detected before shutting off the transmission and setting vfailure flag. this detection shall be done after a guard period set by ttrans from the beginning of the transmission. default value: 0x02 ? 2 * 50 = 100ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 91 12.1.5.24 ttrans register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 ttrans ttrans(7:0) name: ttrans address: 0xfe5b access: read/write reset: 0x2d ? ttrans : this register stores the number of 50 s cycles (clk =20mhz) to wait from the beginning of the transmission before looking for a possible voltage failure. default value: 0x2d ? 45 * 50 = 2.25ms (thus, voltage failures are not expected until the end of chirp signal period) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 92 12.1.5.25 agc0_krssi register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 agc0_krssi agc0_krssi(7:0) name: agc0_krssi address: 0xfe5c access: read/write reset: 0x00 ? agc0_krssi: this register is used to correct rssi (received signal strength indication) computation when automatic gain control 0 (agc0) is active. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 93 12.1.5.26 agc1 krssi register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 agc1_krssi agc1_krssi(7:0) name: agc1_krssi address: 0xfe5d access: read/write reset: 0x00 ? agc 1 _krssi: this register is used to correct rssi (received signal strength indication) computation when automatic gain control 1 (agc 1 ) is active. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 94 12.1.5.27 zero_cross_time registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 zero_cross_time zero_cross_time(19:12) @0xfe69 zero_cross_time (11:4) @0xfe6a zero_cross_time (3:0) ?0000? @0xfe6b ?00000000? @0xfe6c name: zero_cross_time address: 0xfe69 ? 0xfe6c access: read only reset: 0x00, ?, 0x00; ? zero_cross_time : instant in time at which the last zero - cross event took place. it is expressed in 10 s steps and may take values from 0 to 1e6 (20 - bit effective). it is set by hardware and is a read - only register. this register is used by the physical layer for being in accordance with prime specification. it is reserved 32 - bit in data memory to be able to declare as 32 - bit variable. the 20 - bit register msb is aligned to the 32 - bit variable msb, in order to simplify arithmetic calculations with time values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 95 12.1.5.28 zero_cross_config register name bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 b it 0 zero_cross_config -- vezc rezc fezc name: zero_cross_config address: 0xfe6d access: read/write reset: 0x06 ? --: reserved bits ? vezc: virtual edge for zero crossing in this bit is equal to one, the hardware calculates the middle point between two vnr edges to calculate de zero crossing. this mode is used when the vnr signal duty cycle is different from 50%: vecz can be used simultaneously with recz or fecz. using the three of them at a time is not recommended. ? rezc : rising edge for zero crossing if this bit is set to ?1?, the hardware uses the vnr rising edges to calculate zero - crossing. fezc and rezc can be used simultaneously. ? fezc: falling edge for zero crossing if this bit is set to ?1?, the hardware uses the vnr falling edges to calculate zero - c rossing. fezc and rezc can be used simultaneously. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 96 12.1.5.29 psensecycles registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 psensecycles -- flag_psense d(18:16) @0xfe7d d(15:8) @0xfe7e d(7:0) @0xfe7f name: psensecycles address: 0xfe7d ? 0xfe7f access: read/write reset: 0x00, ?, 0x00; ? --: reserved bits ? flag_sense: whenever a new power value is written in psensecycles, flag_psense is set 1 . this flag must be cleared by software ? d(17:0) : power supply consumption measurement the power supply line is sampled ( ? ??? = 20m hz), and the number of logic ?1? detected during nummilis milliseconds is stored in this field in order to calculate power consumption. note: the first valid value is written after nummilis, and then a new valid value is written every nummilis millis econds. note: measurement is only active when a message transmission begins or psense_soft bit is active (see name: 12.1.5.22 ) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 97 12.1.5.30 mean registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 mean -- flag_mean d(18:16) @0xfe80 d(15:8) @0xfe81 d(7:0) @0xfe82 name: psensecycles address: 0xfe80 ? 0xfe82 access: read/write reset: 0x00, ?, 0x00; ? --: reserved bits ? flag_ mean : whenever a new value is written in mean, flag_mean is set to ?1? this flag must be cleared by software ? d(17:0) : this value stores the average power consumption calculated from the value in psensecycles and having into account the convergence factor ?a? (see a_nummilis register in 12.1.5.36 ). note: the first valid value is written after numcycles*nummilis, and then a new valid value is written every nummilis milliseconds www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 98 12.1.5.31 pmax registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 pmax -- flag_pmax d(18:16) @0xfe83 d(15:8) @0xfe84 d(7:0) @0xfe85 name: pmax address: 0xfe83 ? 0xfe85 access: read/write reset: 0x00, ?, 0x00; ? --: reserved bits ? flag_ pmax : whenever a new value is written in pmax, flag_pmax is set to ?1?. this flag must be cleared by software ? d(17:0) : as described in maxpot register (see 12.1.5.34 ), every time the average power consumption exceeds a user defined threshold value, the current transmission is ca ncelled. pmax register stores the average power consumption value that has risen above maxpot threshold. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 99 12.1.5.32 trans_psense register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 trans_psense trans_psense(7:0) name: trans_psense address: 0xfe86 access: read/write reset: 0x2b ? trans_psense : this register stores the number of 50 s cycles to wait from the beginning of a transmission before looking for a possible power failure. this guard time is taken to avoid transient period where the measurement would be inaccurate default value: 0x2b ? 43 * 50 = 2.15ms www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 100 12.1.5.33 p_th registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 p_th -- p_th(18:16) @0xfe87 p_th(15:8) @0xfe88 p_th(7:0) @0xfe89 name: p_th address: 0xfe87 ? 0xfe89 access: read/write reset: 0x07, 0xff, 0xff. ? --: reserved bits ? p_th: these registers contain a user defined power threshold. when the threshold value is exceeded, a low power consumption mode is automatically activated. in this low power consumption mode, the power dissipated in the transistors decreases at the expens e of distortion increasing. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 101 12.1.5.34 maxpot registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 maxpot -- maxpot(18:16) @0xfe8a maxpot (15:8) @0xfe8b maxpot (7:0) @0xfe8c name: maxpot address: 0xfe8a ? 0xfe8c access: read/write reset: 0x07, 0xff, 0xff. ? --: reserved bits ? maxpot: these registers contain a user defined power consumption threshold. when this threshold is exceeded, current transmission is cancelled. when the threshold is exceeded, two flags are activated: ? potfailure flag (see vsense_config in 12.1.5.22 ). this flag indicates that a power failure has occurred. ? flag_pmax flag (see pmax in 12.1.5.31 ). this flag indicates that, after a power failure, the last mean power value measured has been stored in pmax register. to reset both flags is enough to reset either of them, the other will b e automatically reset. this will enable to start new transmissions. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 102 12.1.5.35 numcycles register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 numcycles numcycles(7:0) name: numcycles address: 0xfe8d access: read/write reset: 0x05 ? numcycles : number of cycles of measuring power before obtaining a mean value that can be taken as valid. example1: if numcycles=5(cycles) and nummilis=1(milliseconds), 5 power measurements will be taken during 1 millisecond each one .the first valid power measurement value will be output in the fifth millisecond. example2: if numcycles=3(cycles) and nummilis=20(milliseconds), 3 power measurements will be taken during 20 milliseconds each one. the first valid power measurement value will be output after 60 milliseconds. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 103 12.1.5.36 a_nummilis register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 nummilis -- a(1:0) nummilis(4:0) name: a_nummilis address: 0xfe8e access: read/write reset: 0x21 ? --: reserved bits ? a(1:0): convergence factor averaging factor that sets the convergence speed of the mean calculation algorithm. a=00 sets quicker convergence, while a=11 sets the slowest one. a=01,10 are intermediate values. note: power supply presents high dispersion values, so nummilis value must be take into account in order to select a suitable value for a. if nummilis is high, the mean value can be calculated slowly, because the averaging in being calculated over a long period of time. when nummilis is low, the mean value must be calculated quickly in order to obtain more accurate values. ? nummilis(4:0): measurement acquisition time in milliseconds stores the measurement acquisition time in milliseconds. example1: if numcycles=5(cycles) and nummilis=1(milliseconds), 5 power measurements will be taken during 1 millisecond each one .the first valid power measurement value will be out put in the fifth millisecond. example2: if numcycles=3(cycles) and nummilis=20(milliseconds), 3 power measurements will be taken during 20 milliseconds each one. the first valid power measurement value will be output after 60 milliseconds. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 104 12.1.5.37 emit_config register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 emit_config -- tr_emit two_h_bridges name: emit_config address: 0xfe8f access: read/write reset: 0x03 ? tr_emit : emission mode this bit selects the emission mode (internal drive or external transistors bridge). ? ? 0 ?: emission is done by means of internal sam4sp32a driver. ? ? 1 ?: emission is done by means of external transistors (default). ? two_h_bridges: this bit selects the number of semi - h - bridges in the external interface. ? ? 0 ?: there is only one semi - h - bridge in the ex ternal interface. ? ? 1 ?: there are two semi - h - bridges in the external interface and the field himp (afe_ctl register) determines which one is active (default). semi - h - bridges must be connected following the table below two_h_bridges=?0? two_h_bridges=?1? emit1 p n1 emit2 p n1 emit3 p n1 emit4 n p2 emit5 n p2 emit6 n p2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 105 12.1.5.38 afe_ctl register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 afe_ctl -- himp himp_inv txrx txrx_hard txrx_inv name: afe_ctl address: 0xfe90 access: read/write reset: 0x10 ? --: reserved bits ? himp : analog front end impedance control bit - this bit selects which branch is active when working with a two half - h - bridge branches analog front end. ? ? 0 ?: ?low impedance? half - h - bridge is active (p2 - n2) . ? ? 1 ?: ?high impedance? half - h - bridge is active (p1 - n1) . ? himp_inv : himp pin polarity control this field inverts the polarity of the himp pin output. note: this field only affect to the polarity of the external pin himp output, the value taken from himp bit (afe_ctl(4)) remains unchanged ? txrx : the val ue stored in this bit is taken by the microcontroller in order to set the txrx pin level . ? ? 0 ?: txrx pin output = ?0? . ? ? 1 ?: txrx pin output = ?1? . ? txrx_hard : txrx pin control this field selects if the txrx pin is software/hardware controlled . ? ? 0 ?: txrx pin is software controlled. txrx value is set by txrx bit field (afe_ctl(2)) . ? ? 1 ?: txrx pin is hardware controlled . ? txrx_inv : txrx pin polarity control this field inverts the polarity of the txrx pin output www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 106 12.1.5.39 r registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 r1 r1(7:0) 0xfe9f r2 r2(7:0) 0xfea0 r3 r3(7:0) 0xfea1 r4 r4(7:0) 0xfea2 r5 r5(7:0) 0xfea3 r6 r6(7:0) 0xfea4 r7 r7(7:0) 0xfea5 r8 r8(7:0) 0xfea6 name: r1 ? r8 address: 0xfe9f ? 0xfea6 access: read/write reset: 0x60; 0x60; 0x60; 0x60; 0xff; 0xff; 0xff; 0xff. ? r : t he value in these registers strongly depends on the external circuit configuration. atmel provides values to be used according with the design recommended in sam4sp32a kits please contact atmel power line if different external configuratio ns are going to be used recommended values (according to the configuration recommended in sam4sp32a kits) r1(7:0): 0x21 r2(7:0): 0x20 r3(7:0): 0x12 r4(7:0): 0x02 r5(7:0): 0x37 r6(7:0): 0x77 r7(7:0): 0x37 r8(7:0): 0x77 order of precedence: in the event of a conflict between the ri(7:0) values above and ri(7:0) values specified in the latest documentation in an sam4sp32a kit, the values in the kit documentation shall take precedence. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 107 12.1.5.40 phy_errors registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 phy_errors -- phy_errors(4:0) name: phy_errors address: 0xfe94 access: read/write reset: 0x00 ? --: reserved bits ? phy_errors : physical layer error counter the system stores in these bits the number of times that a physical layer error has occurred. microcontroller can clear this counter to zero. the value stored in this register is cleared every time the register is read. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 108 12.1.5.41 fft_mode registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 fft_mode nsym(5:0) continuous test_mode_en name: fft_mode address: 0xfeb0 access: read/write reset: 0x00 ? nsym : number of symbols to transmit when in continuous transmission mode, symbol data acts as a free - running buffer, increasing from 0 to nsym - 1 and overflowing back to symbol 0. ? continuous: this field enables/disables continuous transmission mode. ? ? 0 ?: continuous transmission mode disabled . ? ? 1 ?: continuous transmission mode enabled . ? test_mode_en: this field enables/disables test mode ? ? 0 ?: test mode disabled . ? ? 1 ?: test mode enabled . configuration for test mode. this register is used by the physical layer to fulfill with prime specification (plme_testmode.request primitive and plme_testmode.confirm primitive, see prime specification). in this mode data provided to fft is written in data memory at addr_phy_ini_tx, codifying each value with 4 bits accor ding to dpsk modulation mapping. the msb of the value is to indicate an input of zero when set to '1'. each byte in data memory contains 2 input values for fft, with the first value located at high bits. there are 97 input values for fft, so many as the nu mber of subcarriers, so there are 48 bytes and a half of the next byte used for codifying them. the other half of this byte (low bits) will be used for the next symbol data. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 109 12.1.5.42 agc_config register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 agc_config -- agc0_pol agc0_value agc0_mode agc1_pol agc1_value agc1_mode name: agc_config address: 0xfeb1 access: read/write reset: 0x24 sam4sp32a has implemented two automatic gain control outputs in order to adjust the received signal level to a suitable range. when in ?automatic? mode, both of them are set to ?1? when the received signal is above 16 - bit - user - definable thresholds (agc1_th and agc0_th) in order to activate external attenuators placed in the external analog front end. the value of these outputs is set duri ng the beginning of a received message and is hold until the end of the message. agc0 and agc1 follow different algorithms, thus using both of them ensures more accurate gain control ? -- : reserved bits ? agc0_pol : agc0 polarity this bit sets the polarit y of the agc0 output. ? ? 0 ?: polarity is inverted . ? ? 1 ?: polarity is not inverted (default) . ? agc0_value: agc0 output value - this bit stores the value wrote by the user to be the agc0 output. this bit is only taken into account when agc0 ?forced? mode is ac tive (agc0_mode=?1?). agc0_pol field can invert this value. ? agc0_mode : agc0 mode this bit selects which agc0 mode is being used ? ? 0 ?: ?automatic? mode. agc0 output will be managed by the mac, depending on saturation detected in received signal. if saturation is detected, agc0 output will be ?1?. else, agc0 output will be ?0?. agc0_pol field can invert this value. (see sat_th register s in 12.1.5.43 ) ? ? 1 ?: ?forced? mode. agc0 output will be managed by the user, according to the value wrote in agc0_value field (agc_config(4)). ? agc1_pol : agc 1 polarity this bit sets the polarity of the ag c1 output. ? ? 0 ?: polarity is inverted . ? ? 1 ?: polarity is not inverted (default) . ? agc 1 _value: agc 1 output value - this bit stores the value wrote by the user to be the agc 1 output. this bit is only taken into acco unt when agc 1 ?forced? mode is active (agc 1 _mode=?1?). agc 1 _pol field can invert this value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 110 ? agc1_mode : agc 1 mode this bit selects which agc 1 mode is being used ? ? 0 ?: ?automatic? mode. agc 1 output will be managed by the mac, depending on saturation detected in received signal. if saturation is detected, agc 1 output will be ?1?. else, agc 1 output will be ?0?. agc 1 _pol field can invert this value. (see sat_th register s in 12.1.5.43 ) ? ? 1 ?: ?fo rced? mode. agc 1 output will be managed by the user, according to the value wrote in agc 1 _value field (agc_config(4)). www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 111 12.1.5.43 sat_th registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 sat_th sat_th(15:8) @0xfeb7 sat_th(7:0) @0xfeb8 name: sat_th address: 0xfeb7 ? 0xfeb8 access: read/write reset: 0x40; 0x00 ? sat_th : these registers store a threshold for the plc input - signal amplitude. if this threshold is exceeded, agc thresholds (agc0_th and agc1_th) will be taken into account. if this threshold is not exceeded, agc0_th and agc1_th thresholds will be ignored, thus the agc algorithm will be never triggered. recommended value for atmel reference design = 0x37aa. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 112 12.1.5.44 agc1_th registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 agc1_th agc1_th(15:8) @0xfe5f agc1_th(7:0) @0xfe60 name: agc1_th address: 0xfe5f ? 0xfe60 access: read/write reset: 0x40; 0x00 ? agc1_th : agc1 threshold these registers store the 16 - bit upper threshold used by the agc1 algorithm to determine that the input signal must be attenuated. this threshold is only taken into account in agc1 ?automatic? mode (agc_config.agc1_mode=?0?). this threshold is only taken into account if sat_th value is exceeded. recommended value for atmel reference design = 0x4a00. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 113 12.1.5.45 agc0_th registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 b it 0 agc0_th agc0_th(15:8) @0xfeb2 agc0_th(7:0) @0xfeb3 name: agc0_th address: 0xfeb2 ? 0xfeb3 access: read/write reset: 0x10; 0x00 ? agc0_th : agc 0 threshold these registers store the 16 - bit upper threshold used by the agc0 algorithm to determine that the input signal must be attenuated. this threshold is only taken into account in agc0 ?automatic? mode (agc_config.agc0_mode=?0?). this threshold is only taken into account if sat_th value is exceeded. recommended value for atmel reference design = 0x1000. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 114 12.1.5.46 agc_pads register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 agc_pads -- p46_mode switch_agc name: agc_pads address: 0xfe61 access: read/write reset: 0x00 ? -- : reserved bits ? p46_mode : this field controls the p4.6/t2/agc1 output pin (pin no.94). ? ? 0 ?: pin no.94 works as p4.6/t2 output pin . ? ? 1 ?: pin no.94 works as agc1 output pin . ? switch_agc: this bit switches the agc0 and agc1 outputs. ? ? 0 ?: not switched agc outputs . ? ? 1 ?: switched agc outputs . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 115 12.2 sam4sp32a mac layer the sam4sp32a hardware mac layer consists of a hardware implementation of s ome functionalities of the mac layer entity specified in prime specification. these features are crc calculation and aes128 block. figure 12 - 9. sam4sp32a software stack diagram atmel prime stack implements by software the rest of the mac layer requirements and capab ilities. furthermore, the software package allows the communication with the management plane by means of the two access points described by prime (phy layer management entity sap and mac layer management entity sap ) and the interface to communicate mac la yer with the upper layer (convergence layer). please check the ?atmel prime stack user manual? for software package detailed description and functionality. 12.2.1 cyclic redundancy check (crc) there are three types of mac pdus (generic, promotion and beacon) for different purposes , a nd each one has its own specific crc. in sam4sp32a there is a hardware implementation of every crc type calculated by the mac layer. this crc hardware - calculation is enabled by default . note that the crc included at the physical l ayer is also a hardware implementation available in sam4sp32a and it is also enabled by default . convergence layer (cl) media access control (mac) layer physical (phy) layer aes crc hardware software stack provided by atmel mlme-sap plme-sap mac-sap phy-sap management plane control and data plane mac layer management entity phy layer management entity www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 116 figure 12 - 10. generic mac pdu format and generic mac header detail in transmission all crc bytes are real - time calculated and the last bytes of the mac pdu are overwritten with these values, (provided that the field ht in the first byte of the mac header in transmission data is equal to the corresponding mac pdu type ) . i n reception the crc bytes are also real - time calculated and these bytes are checked with the last by tes of the mac pdu. if the crc is not correct , then an error flag is activated , the complete frame is discarded, and the corresponding error counter is incr eased. these counters allow the mac layer to take decisions according to error ratio. for the generic mac pdu , there is an 8 - bit crc in the generic mac header, which corresponds to prime hdr.hcs . in reception if this crc doesn?t check successfully, the cur rent frame is discarded and no interruption is generated. this works in the same way as crc for the phy layer (crc ctrl, located in the phy header , see prime specification for further information ) . there is another crc for the generic mac pdu which is the last field of the gpdu. it is 32 bits long and i t is used to detect transmission errors. the crc shall cover the concatenation of the sna with the gpdu except for the crc field itself. in reception, if the crc is not successful then an internal flag is se t and the error counter is increased . for the promotion needed pdu there is an 8 - bit crc, calculated with the first 13 bytes of the header. in reception, if this crc is not correct , then an internal flag is set and the corresponding error counter is increa sed . for the beacon pdu there is a 32 - bit crc calculated with the same algorithm as the one defined for the crc of the generic mac pdu. this crc shall be calculated over the complete bpdu except for the crc field itself. in reception, if this crc is not successful, then an internal flag is set and the same error counter as for gpdu is increased. the hardware used for this crc is the same as the one used for gpdu. generic mac header packet 1 packet n crc unused hdr.hcs hdr.ht reserved reserved hdr.do hdr.level msb lsb www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 117 12.2.2 advanced encryption standard (aes) one of the security functionalities in prime is the 128 - bit aes encryption of data and its associated crc. sam4sp32a includes a hardware implementation of this block, and it is used by the physical layer in real - time transmission/reception. it is possible to use this block externally as a peripheral unit, by ac cessing the specific registers designed to control it. therefore there are some configurable parameters and input/output buffers to the block. figure 12 - 11. phy layer transmitter block diagram there are two basic operation ways in sam4sp32a when using prime security profile 1. the first one is real - time encryption and the second one is independent encryption from the phy layer. real - time encryption: the aes128 core is integrated in the physical chain, and data is encrypted and decrypted in real - time when needed. in t ransmission, data is transferred to the emission buffer by means of the dma tx channel . t hen the 128 bits located in the buffer are encrypted before starting transmission (note that beacon pdu, promotion pdu and generic mac header , as well as several contr ol packets, are not encrypted). data is extracted when required from this buffer until it is empty, and then a new dma transfer is requested to fill the 16 bytes and a new encryption is executed. the key used for encryption must be set at the corresponding register, and it can vary from a packet to another. in reception, data is obtained from the phy layer and it is passed to the aes128 block. when the reception buffer is full with incoming data , the 128 bits are decrypted and transferred to external memory through dma rx channel. then the reception buffer is available again to fill with processed data. the header is always real - time analyzed in order to know if encryption process must be applied. independent encryption: the aes128 core is used as a peripher al unit, accessible with several registers mapped in external memory. in this mode, when in transmission, data must be encrypted previously to the use of the phy_data.request primitive (see prime specification), in an independent way. in reception, data pa ssed by the phy layer is already encrypted and must be decrypted in a subsequent process. when working with aes block as a peripheral unit, automatic crc calculation by hardware is disabled. crc convolutional encoder scrambler interleaver sub-carrier modulator ifft cyclix prefix (?) aes block (?) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 118 12.2.3 mac layer registers 12.2.3.1 sna registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 sna sna(47:40) @fe62 ? ? sna(7: 0) @fe67 name: sna address: 0xfe62 ? 0xfe67 access: read/write reset: 0x00, ?, 0x00 ? sna : sub network address these registers store the 48 - bit sub network address. when the system sub network address is available, the sam4sp32a microcontroller must write it down so the phy layer will be able to correctly calculate the crc?s, which depend on this parameter . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 119 12.2.3.2 vite rbi_ber_hard register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 viterbi_ber_hard viterbi_ber_hard(7:0) name: viterbi_ber_hard address: 0xfe36 access: read only reset: 0x00 ? viterbi_ber_hard : this register stores the number of errors accumulated in a message reception using viterbi hard* de cis ion. the value is cleared by hardware each time a new message is received. *hard de cis ion: in ?hard? detection there are only two decision levels. if the received value is different than the corrected one, the error value taken is ?1?. otherwise, the error value taken is ?0?. figure 12 - 12. viterbi hard detection decision levels from the value in viterbi_ber_hard register it is possible to calculate de bit error rate according to the following formula: ber = 10 ??? _ ??? _ ???? 40 ? 1 100 ? 0? ?1? strong ?1? weak ?1? weak ?0? strong ?0? 1 0 decision levels www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 120 12.2.3.3 viterbi_ber_soft register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 viterbi_ber_soft viterbi_ber_soft(7:0) name: viterbi_ber_soft address: 0xfe37 access: read only reset: 0x00 ? viterbi_ber_soft : this register stores a value proportional to the number of errors accumulated in a message reception using viterbi soft* decis ion. the value is cleared by hardware each time a new message is received. *soft decision: in ?soft? decision there are fifteen decision levels. a strong ?0? is represented by a value of ?0?, while a strong ?1? is represented by a value of ?15?. the rest of values are intermediate, so ?7? is used to represent a weak ?0? and ?8? represents a weak ?1?. soft decision calculates the er ror in one bit received as the distance in decision levels between the value received (a value in the range 0 to 15) and the corrected one (0 or 15). figure 12 - 13. viterbi hard detection decision levels ?0? ?1? strong ?1? weak ?1? weak ?0? strong ?0? 15 0 decision levels 7 8 ... ... www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 121 12.2.3.4 err_crc32_mac registers name bit 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bit 1 b it 0 err_crc32_mac err_crc32_mac(15:8) @0xfeba err_crc32_mac(7:0) @0xfebb name: err_crc32_mac address: 0xfeba ? 0xfebb access: read/write reset: 0x00, 0x00 ? err_crc32_mac: 16- bit value that stores the number of received messages that have been discarded by an error in the mac layer crc32. n ote: to clear this value, these registers must be reset by the sam4sp32a microcontroller . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 122 12.2.3.5 err_crc8_mac registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 err_crc8_mac err_crc8_mac(15:8) @0xfebc err_crc8_mac(7:0) @0xfebd name: err_crc8_mac address: 0xfebc ? 0xfebd access: read/write reset: 0x00, 0x00 ? err_crc 8 _mac: 16- bit value that stores the number of received messages that have been discarded by an error in the payload mac layer crc8. note: to clear this value, these registers must be reset by the sam4sp32a microcontroller . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 123 12.2.3.6 err_crc 8_ aes registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 err_crc8_aes err_crc8_aes(15:8) @0xfebe err_crc8_aes(7:0) @0xfebf name: err_crc8_aes address: 0xfebe ? 0xfebf access: read/write reset: 0x00, 0x00 ? err_crc 8 _ aes : 16- bit value that stores the number of received messages that have been discarded by an error in the payload aes crc8. note: to clear this value, these registers must be reset by the sam4sp32a microcontroller . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 124 12.2.3.7 err_crc8_mac_hd registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 err_crc8_mac_hd err_crc8_mac_hd(15:8) @0xfec0 err_crc8_mac_hd(7:0) @0xfec1 name: err_crc8_mac_hd address: 0xfec0 ? 0xfec1 access: read/write reset: 0x00, 0x00 ? err_crc 8 _ mac_hd : 16 - bit value that stores the number of received messages that have been discarded by an error in the header mac layer . note: to clear this value, these registers must be reset by the sam4sp32a microcontroller . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 125 12.2.3.8 err_crc8_phy registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 err_crc8_phy err_crc8_phy(15:8) @0xfec2 err_crc8_phy(7:0) @0xfec3 name: err_crc8_aes address: 0xfec2 ? 0xfec3 access: read/write reset: 0x00, 0x00 ? err_crc 8 _ phy : 16- bit value that stores the number of received messages that have been discarded by an error in the phy layer crc8. note: to clear this value, these registers must be reset by the sam4sp32a microcontroller . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 126 12.2.3.9 false_det_config register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 false_det _config -- err_crc8 _mac invalid _protocol error _len error_pad _len unknown _pdu unknown _sp name: false_det_config address: 0xfec4 access: read/write reset: 0x10 ? --: reserved bits ? err_crc8_mac : if this bit is set to 1 , false_det registers will increase its error counter if a received message has a correct phy layer crc8 but the mac layer crc8 present in its header is wrong . ? invalid_protocol: if this bit is set to 1 , false_det registers will increase its error counter if a receive d message has a correct phy layer crc8 but the protocol field indicates a modulation not supported by the system . ? error_len : if this bit is set to 1 , false_det registers will increase its error counter if a received message has a correct phy layer crc8 but the len field indicates a not valid message length . ? error_pad_len: if this bit is set to 1 , false_det registers will increase its error counter if a received message has a correct phy layer crc8 but the pad_ len field indicates a not valid message padding l ength . ? unknown_pdu: if this bit is set to 1 , false_det registers will increase its error counter if a received message has a correct phy layer crc8 but the ht field indicates a header type different from beacon, promotion or generic . ? unknown_sp: if this b it is set to 1 , false_det registers will increase its error counter if a received message has a correct phy layer crc8 but the security_protocol field is wrong. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 127 12.2.3.10 false_det registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 false_det false_det(15:8) @0xfec5 false_det(7:0) @0xfec6 name: false_det address: 0xfec5 ? 0xfec6 access: read/write reset: 0x00, 0x00 ? false_det : erroneous non - discarded messages. 16- bit value that stores the number of received messages that have not been discarded since its phy layer crc8 is correct, but in which there are other incorrect field s . the fields that shall be taken into account to increase the counter in case they were wrong can be selected by false_det_config register. note: to clear this value, these registers must be reset b y the sam4sp32a microcontroller www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 128 12.2.3.11 max_len_dbpsk register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 max_len_dbpsk -- max_len_dbpsk(5:0) name: max_len_dbpsk address: 0xfec8 access: read/write reset: 0xff ? --: reserved bits ? max_len_dbpsk : this register set s the maximum length, measured in ofdm symbols, that the system allows to receive when working with dbpsk modulation and no viterbi encoding. if a message in such modulation/encoding is received and its len field indicates a length above the threshold defin ed by max_len_dbpsk value, the message will be discarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 129 12.2.3.12 max_len_dbpsk_vtb register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 max_len_dbpsk_vtb -- max_len_dbpsk_vtb(5:0) name: max_len_dbpsk_vtb address: 0xfec9 access: read/write reset: 0xff ? --: reserved bits ? max_len_dbpsk_vtb : this register set s the maximum length, measured in ofdm symbols that the system allows to receive when working with dbpsk modulation and viterbi encoding. if a message in such modulation/encoding is received and its len field indicates a length above the threshold defined by max_len_dbpsk_vtb value, the message will be discarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 130 12.2.3.13 max_len_dqpsk register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 max_len_dqpsk -- max_len_dqpsk(5:0) name: max_len_dqpsk address: 0xfeca access: read/write reset: 0xff ? --: reserved bits ? max_len_dbpsk : this register set s the maximum length, measured in ofdm symbols, that the system allows to receive when working with d q psk modulation and no viterbi encoding. if a message in such modulation/encoding is received and its len fi eld indicates a length above the threshold defined by max_len_d q psk value, the message will be discarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 131 12.2.3.14 max_len_dqpsk_vtb registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 max_len_dqpsk_vtb -- max_len_dqpsk_vtb(5:0) name: max_len_dqpsk_vtb address: 0xfecb access: read/write reset: 0xff ? --: reserved bits ? max_len_dqpsk_vtb : this register set s the maximum length, measured in ofdm symbols that the system allows to receive when working with d q psk modulation and viterbi encoding. if a message in such modulation/encoding is received and its len field indicates a length above the threshold defined by max_len_d q psk _vtb value, the message will be discarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 132 12.2.3.15 max_len_d8psk registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 max_len_d8psk -- max_len_d8psk(5:0) name: max_len_d8psk address: 0xfecc access: read/write reset: 0xff ? --: reserved bits ? max_len_d8psk : this register set s the maximum length, measured in ofdm symbols, that the system allows to receive when working with d 8 psk modulation and no viterbi encoding. if a message in such modulation/encoding is received and its len field indicates a length above the threshold defined by max_len_d 8 psk value, the message will be discarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 133 12.2.3.16 max_len_d 8 psk_vtb register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 max_len_d8psk_vtb -- max_len_d8psk_vtb(5:0) name: max_len_d8psk_vtb address: 0xfecd access: read/write reset: 0xff ? --: reserved bits ? max_len_d8psk_vtb : this register set s the maximum length, measured in ofdm symbols that the system allows to receive when working with d 8 psk modulation and viterbi encoding. if a message in such modulation/encoding is received and its len field indicates a length above the threshold defined by max_len_d 8 psk _vtb value, the message will be discarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 134 12.2.3.17 aes_pad_len register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 aes_pad_len -- aes_pad_len(3:0) name: aes_pad_len address: 0xfe25 access: read/write reset: 0x00 ? --: reserved bits ? aes_pad_len : aes protocol works over 16 - bytes - lenght blocks. when a block is not 16 - bytes long, this register indicates the number of padding bytes to append. this register takes values between 0 and 15. in transmission, if encryption is being used, microcontroller must write th e aes padding length in this register. in no - encrypted transmission and in reception, the value in this register is not used . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 135 12.2.3.18 aes_data_in registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 aes_data_in aes_data_in(127:120) @ffa0 ? ? aes_data_in(7: 0) @ffaf name: aes_data_in address: 0xffa0 ? 0xffaf access: read/write reset: 0x00, ?, 0x00 ? aes_data_in : input buffer for aes128 block. this buffer can be written to be encrypted/decrypted by the key in key_periph (see 12.2.3.20 ) register . the resulting data could be read at aes_data_out (see 12.2.3.19 ) registers . www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 136 12.2.3.19 aes_data_out registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 aes_data_out aes_data_out(127:120) @ffb0 ? ? aes_data_out(7: 0) @ffbf name: aes_data_out address: 0xffb0 ? 0xffbf access: read only reset: 0x00, ?, 0x00 ? aes_data_out : outp ut buffer for aes128 block. this buffer stores the result of the encryption/decryption processing of data in aes_data_in (see 12.2.3.18 ) register with the key in key_periph (see 12.2.3.20 ) register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 137 12.2.3.20 key_periph registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 key_periph key_periph(127:120) @ffc0 ? ? key_p eriph (7: 0) @ffcf name: key_periph address: 0xffc0 ? 0xffcf access: read/write reset: key_periph(127:120) : 0x00; key_periph(119:112) : 0x01; key_periph(111:104) : 0x02; key_periph(103:96) : 0x03; key_periph(95:88) : 0x04; key_periph(87:80) : 0x05; key_periph(79:72) : 0x06; key_periph(71:64) : 0x07; key_periph(63:56) : 0x08; key_periph(55:48) : 0x09; key_periph(47:40) : 0x0a; key_periph(39:32) : 0x0b; key_periph(31:24) : 0x0c; key_periph(23:16) : 0x0d; key_periph(15:8) : 0x0e; key_periph(7:0) : 0x0f; ? key_periph : key for aes128 block when used as peripheral part . this key is used for encrypting/decrypting data in aes_data_in registers. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 138 12.2.3.21 key_phy registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 key_phy key_phy(127:120) @ffd0 ? ? key_phy(7: 0) @ffdf name: key_phy address: 0xffd0 ? 0xffdf access: read/write reset: key_phy(127:120): 0x00; key_phy(119:112) : 0x01; key_phy(111:104) : 0x02; key_phy(103:96) : 0x03; key_phy(95:88) : 0x04; key_phy(87:80) : 0x05; key_phy(79:72) : 0x06; key_phy(71:64) : 0x07; key_phy(63:56) : 0x08; key_phy(55:48) : 0x09; key_phy(47:40) : 0x0a; key_phy(39:32) : 0x0b; key_phy(31:24) : 0x0c; key_phy(23:16) : 0x0d; key_phy(15:8) : 0x0e; key_phy(7:0) : 0x0f; ? key_phy : key for aes128 block when used by the physical layer this key is used in real time encryption/decryption for security profile 1. when any of the dma channels of the physical layer accesses to the memory, then this key and the input data are multiplexed to the aes128 - core. also outp ut data is multiplexed in order to provide encrypted/decrypted data to the physical buffer. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 139 12.2.3.22 aes_sfr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 aes_sfr -- ready start cipher name: aes_sfr address: 0xffe0 access: read/write reset: 0x00 ? -- : reserved bits. ? ready : flag to indicate encryption/decryption process completion. when the encryption/decryption has been completed, this flag is set to ?1?. this flag is automatically cleared when an encryption/decryption process begins. ? start: when this bit is set to ?1?, th e encryption/decryption process is triggered. if encryption/decryption starts successfully, then this bit is automatically cleared to ?0?. ? cipher: this field indicates if data must be encrypted or decrypted. ? ? 0 ? - decryption mode ? ? 1 ? - encryption mode www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 140 13. e lectrical characteristics 13.1 absolute maximum ratings permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions given in the recommended operating conditions section. exposure to t he absolute maximum conditions for extended periods may affect device reliability. table 13 - 1. sam4sp32a absolute maximum ratings parameter symbol rating unit operating temperature (industrial) ot - 40 to +85 oc storage temperature tst - 55 to 125 oc voltage on input pins with respect to ground -- - 0.3 to +4.0 v maximum operating voltage (vddcore) vddcore max 1.32 v maximum operating voltage (vddio) vddio max 4.0 v junction temperature tj - 40 to 125 oc total dc output curren t on all i/o lines io 300 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 141 13.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = - 40 o c to +85 o c, unless otherwise specified. table 13 - 2. sam4sp32a dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 1.08 1.20 1.32 v v vddio dc supply i/os (1) (2) 3.00 3.30 3.60 v vddpll plla, pllb and main oscillator suplly 1.08 -- 1.32 a vdd plc analog converter power supply 3.00 3.30 3.60 v il input low - level voltage pa0 - pa25, pb0 - pb12, pc0, pc5, pc26 - 0.3 min[0.8v:0.3 x v vddio ] v ih input high - level voltage pa0 - pa25, pb0 pb12, pc0, pc5, pc26 min[2.0v:0.7 x v vddio ] v vddio + 0.3v v oh output high - level voltage pa0 - pa25, pb0 - pb12, pc0, pc5, pc26 i ol = 4.0 ma v vddio - 0.4v vddio [3.0v : 3.60v] pb0 - pb12 v vddio - 0.15v v ol output low - level voltage pa0 - pa25, pb0 pb12, pc0, pc5, pc26 i ol = 4.0 ma 0.4 vddio [3.0v : 3.60v] pb0 - pb12 0.15 v hys hysteresis voltage pa0 - pa25, pb0 - pb9, pb12, pc0,pc5,pc26 (hysteresis mode enabled) 150 mv i oh i oh (or i source ) vddio [3v : 3.60v] ;v oh = v vddio - 0.4v - pa14 (spck) - pa[12 - 13], - pa[0 - 3] - other pins (1) vddio [3.0v : 3.60v] - pb[10 - 11] - emit[1:6] - other plc pins - 4 - 4 - 2 - 2 - 30 - 20 - 10 ma vddio [3v : 3.60v] ; v oh = v vddio - 0.4v - nrst - 2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 142 table 13 - 2. sam4sp32a dc characteristics (continued) symbol parameter conditions min typ max units i ol i ol (or i sink ) vddio [3v : 3.60v] ;v oh = v vddio - 0.4v - pa14 (spck) - pa[12 - 13], - pa[0 - 3] - other pins (1) vddio [3.0v : 3.60v] - pb[10 - 11] - emit[1:6] - other plc pins 4 4 2 2 30 20 10 vddio [3v : 3.60v] ; v oh = v vddio - 0.4v - nrst 2 i il input low pull_up off - 1 1 a pull_up on 10 50 i i h input high pull_up off - 1 1 pull_up on 10 50 r pullup internal pull - up resistor pa0 - pa25, pb0 - pb12, pc0, pc5, pc26, nrst 70 100 130 k? r pulldown internal pull - down resistor pa0 - pa25, pb0 - pb12, pc0, pc5, pc26, nrst 70 100 130 plc rpu plc internal pull - up resistor 3.3v i/o 10 33 80 plc rpd plc internal pull - down resistor 3.3v i/o 10 33 80 note: 1. at power - up vddio needs to reach 0.6v before vddin reaches 1.0v 2. vddio voltage needs to be equal or below to (vddin voltage +0.5v) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 143 table 13 - 3. 1.2v voltage regulator characteristics (vddout12) symbol parameter conditions min typ max units v vddin dc input voltage range (4)(5) 1.6 3.3 3.6 v v vddout dc output voltage normal mode standby mode 1.2 0 v v accuracy output voltage accuracy i load = 0.8ma to 80 ma (after trimming) - 3 3 % i load i load - start maximum dc output current maximum peak current during startup v vddin > 1.8v v vddin 1.8v 80 40 ma see note (3) 400 ma d dropout dropout voltage v vddin = 1.6v, i load = max 400 mv v line v line - tr line regulation transient line regulation v vddin from 2.7v to 3.6v; i load max v vddin from 2.7v to 3.6v; tr = tf = 5s; i load max 10 50 30 150 mv v load v load - tr load regulation transient load regulation v vddin 1.8v; i load = 10% to 90% max v vddin 1.8v; i load = 10% to 90% max tr = tf = 5 s 20 50 40 150 mv i q quiescent current normal mode; @ i load = 0 ma @ i load = 80 ma standby mode; 5 500 1 a cd in input decoupling capacitor cf. external capacitor requirements (1) 4.7 f cd out output decoupling capacitor cf. external capacitor requirements (2) esr 1.85 0.1 2.2 5.9 10 f ? t on turn on time cd out = 2.2f, v vddout reaches 1.2v (+/ - 3%) 300 s t off turn off time cd out = 2.2f 40 ms www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 144 note: 1. a 10f or higher ceramic capacitor must be connected between vddin and the closest gnd pin of the device. this large decoupling capacitor is mandatory to reduce startup current, improving transient response and noise rejection. 2. to ensure stability, an external 2.2f output capacitor, cdout must be connected between the vddout and the closest gnd pin of the device. the esr (equivalent series resistance) o f the capacitor must be in the range 0.1 to 10 ohms. solid tantalum and multilayer ceramic capacitors are all suitable as output capacitor. a 100nf bypass capacitor between vddout and the closest gnd pin of the device helps decreasing output noise and improves the load transient response. 3. defined as the current needed to charge external bypass/decoupling capacitor network. 4. at power - up vddio needs to reach 0.6v before vddin reaches 1.0v 5. vddio voltage needs to be equal or below to (vddin voltage +0.5v) table 13 - 4. core power supply brownout detector characteristics parameter symbol conditions min typ max units supply falling threshold (1) v th - 0.98 1.0 1.04 v hysteresis v hyst 110 mv supply rising threshold v th+ 0.8 1.0 1.08 v current consumption on vddcoare i ddon brownout detector enabled 24 a i ddoff brownout detector disable 2 current consumption on vddio i dd33on brownout detector enabled 24 i dd33off brownout detector disable 2 v th - detection propagation time td - [ - 40/+85 o c] - 2.5 +2.5 % start time t start from disable state to enable state 320 s note: 1. the product is guaranteed to be functional at v th - www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 145 figure 13 - 1. core brownout output waveform table 13 - 5. vddio supply monitor parameter symbol conditions min typ max units supply monitor threshold v th 16 selectable steps 1.6 3.34 v threshold level accuracy t accuracy [ - 40/+85 o c] - 2.5 +2.5 % hysteresis v hyst 20 30 mv current consumption on vddcoare i ddon enabled 40 a i ddoff disable 10 start time t start from disable state to enable state 320 s t vdd c ore v th- v th+ bod output t t d+ t d- www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 146 table 13 - 6. threshold selection digital code threshold min (v) threshold typ (v) threshold max (v) 0000 1.58 1.6 1.62 0001 1.7 1.72 1.74 0010 1.82 1.84 1.86 0011 1.94 1.96 1.98 0100 2.05 2.08 2.11 0101 2.17 2.2 2.23 0110 2.29 2.32 2.35 0111 2.41 2.44 2.47 1000 2.53 2.56 2.59 1001 2.65 2.68 2.71 1010 2.77 2.8 2.83 1011 2.8 2.92 2.95 1100 3.0 3.04 3.07 1101 3.12 3.16 3.2 1110 3.24 3.28 3.32 1111 3.36 3.4 3.44 figure 13 - 2. vddio supply monitor v th v h y st vddio r eset v th + www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 147 table 13 - 7. zero - power - on reset characteristics parameter symbol coditions min typ max units threshold voltage rising v th + at startup 1.45 1.53 1.59 v threshold voltage falling v th - 1.35 1.45 1.55 v reset time - out period tres 100 240 500 s figure 13 - 3. zero - power - on reset characteristics table 13 - 8. dc flash characteristics parameter symbol coditions typ max units active current i cc random 144 - bit read: maximum read frequency onto vddcore = 1.2 @ 25 o c 16 25 ma random 72 - bit read: maximum read frequency onto vddcore = 1.2 @ 25 o c 10 18 program onto vddcore = 1.2v @ 25 o c 3 5 v th- v th+ vddio r eset www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 148 13.3 power consumption ? power consumption of the device according to the different low power mode capabilities (backup, wait, sleep) and active mode. ? power consumption on power supply in different modes: backup, wait, sleep and active. ? power consumption by perip heral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 13.3.1 backup mode current consuption the backup mode configuration and measurements are defined as follows. figure 13 - 4. measurement setup 13.3.1.1 configuration a ? supply monitor on vddio is disabled ? rtt and rtc not used ? embedded slow clock rc oscillator used ? one wkupx enabled ? current measurement on amp1 (see figure 13 - 4 ) 13.3.1.2 c onfiguration b ? supply monitor on vddio is disabled ? rtt used ? one wkupx enabled ? current measurement on amp1 (see figure 13 - 4 ) ? 32 khz crystal oscillator used vddio vddout12 vdd c ore vddin v oltage r egul a t or vddpll 3.3v a mp1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 149 table 13 - 9. power consumption for backup mode configuration a and b conditions total consumption (amp1) configuration a total consumption (amp1) configuration b unit vddio = 3.3v @25c vddio = 3.0v @25c vddio = 2.5v @25c vddio = 1.8v @25c 1.98 1.79 1.51 1 1.85 1.66 1.37 0.95 a vddio = 3.3v @85c vddio = 3.0v @85c vddio = 2.5v @85c vddio = 1.8v @85c 13.0 12.0 10.5 8.78 12.42 11.42 10.05 8.42 a 13.3.2 sleep and wait mode current consumption the wait mode and sleep mode configuration and measurements are defined below. figure 13 - 5. measurement setup for sleep mode 13.3.2.1 sleep mode ? core clock off ? master clock (mck) running at various frequencies with plla or the fast rc oscillator. ? fast start - up through wkup0 - 15 pins ? current measurement as shown in figure figure 13 - 6 ? all peripheral clocks deactivated table 13 - 10 below gives current consumption in typical conditions. vddio vddout12 vdd c ore vddin v oltage r egul a t or vddpll 3.3v a mp1 a mp2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 150 table 13 - 10. typical current consumption for sleep mode conditions vddcore consumption (amp1) total consumption (amp2) unit figure 13 - 6 @25c mck = 48 mhz there is no activity on the i/os of the device. 2.52 3.04 ma figure 13 - 6. current consumption in sleep mode (amp1) versus master clock ranges (condition from table 13 - 10 ) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 151 table 13 - 11. sleep mode current consumptionversus master clock (mck) variation with plla core clock/mck (mhz) vddcore consumption (amp1) total consumption (amp2) unit 120 8.1 9.9 ma 100 6.7 8.3 ma 84 5.7 7.1 ma 64 4.5 6.4 ma 48 3.4 4.8 ma 32 2.3 3.38 ma 24 1.8 3.31 ma 13.3.2.2 wait mode figure 13 - 7. measurement setup for wait mode ? core clock and master clock stopped ? current measurement as shown in the above figure ? all peripheral clocks deactivated table 13 - 12 gives current consumption in typical conditions. vddio vddout12 vdd c ore vddin v oltage r egul a t or vddpll 3.3v a mp1 a mp2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 152 table 13 - 12. typical current consumption in w ait mode conditions vddout consumption (amp1) total consumption (amp2) unit see figure 13 - 7 @25c there is no activity on the i/os of the device. with the flash in standby mode 20.4 32.2 a see figure 13 - 7 @25c there is no activity on the i/os of the device. with the flash in deep power down mode 20.5 27.6 a 13.3.3 active mode power consumption the active mode configuration and measurements are defined as follows: ? vddio = vddin = 3.3v ? vddcore = 1.2v (internal voltage regulator used) ? t a = 25 c ? application running from flash memory with128 - bit access mode ? all peripheral clocks are deactivated. ? master clock (mck) running at various frequencies with plla or the fast rc oscillator. ? current measurement on amp1 (vddcore) and total current on amp2 figure 13 - 8. active mode measurement setup tables below give active mode current consumption in typical conditions. ? vddcore at 1.2v ? temperature = 25c vddio vddout12 vdd c ore vddin v oltage r egul a t or vddpll 3.3v a mp1 a mp2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 153 table 13 - 13. active power consumption with vddcore @ 1.2v (vddout12) running from flash memory or sram core clock (mhz) coremark unit 128- bit flash access (1) 64- bit flash access (1) amp1 amp2 amp1 amp2 ma 120 24.9 28.8 18 21.4 100 21.9 25.4 16.3 19.5 84 18.5 21.4 13.8 16.6 64 15.0 17.6 11.4 13.9 48 11.9 14.3 9.6 11.8 32 8.1 9.9 7.4 9.3 24 6.0 7.7 5.8 7.5 12 3.4 6.1 3.2 6.0 8 2.3 4.5 2.2 4.5 4 1.2 2.6 1.2 2.9 2 0.7 1.9 0.7 2.0 1 0.4 1.3 0.4 1.6 0.5 0.3 1.1 0.3 1.3 note: 1. flash wait state (fws) in eefc_fmr adjusted versus core frequency www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 154 13.3.4 peripheral power consumption in active mode table 13 - 14. power consumption on v vddcore (1) (when prime plc transceiver is turned off) peripheral consumption (typ) unit pio controller a (pioa) 5.6 a/mhz pio controller b (piob) 7.5 pio controller c (pioc) 5.9 uart 3.8 usart 7.7 pwm 10.5 twi 5.8 plc_bridge 6.9 timer counter (tcx) 4.7 acc 1.3 crccu 1.4 smc 3.6 ssc 6.1 udp 5 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 155 table 13 - 15. prime plc transceiver peripheral power consumption parameter condition symbol rating unit min. typ. max. powe r consumption (2) p 25 -- 260 -- mw power consumption (worst case) (3) p 85 -- -- 355 -- note: 1. vddio = 3.3v, v vd dcore = 1.08v, t a = 25 c 2. vddio = 3.3v, v vd dcore = 1.08v, t a = 25c 3. vddio = 3.3v, v vd dcore = 1.08v, t a = 25c www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 156 13.4 oscillator characteristics 13.4.1 32 khz rc oscillator characteristics table 13 - 16. 32 khz rc oscillator characteristics symbol parameter conditions min typ max unit rc oscillator frequency 20 32 44 khz frequency supply dependency - 3 3 %/v frequency temperature dependency over temperature range ( - 40c/ +85c) versus 25c - 7 7 % duty duty cycle 45 50 55 % t on startup time 100 s i ddon current consumption after startup time temp. range = - 40c to +125c typical consumption at 2.2v supply and temp = 25c 540 860 na www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 157 13.4.2 4/8/12 mhz rc oscillators characteristics table 13 - 17. 4/8/12 mhz rc oscillators characteristics symbol parameter conditions min typ max unit f range rc oscillator frequency range (1) 4 12 mhz acc 4 4 mhz total accuracy - 40c a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 159 13.4.4 32.768 khz crystal characteristics table 13 - 19. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor (r s) crystal @ 32.768 khz 50 100 k ? c m motional capacitance crystal @ 32.768 khz 0.6 3 ff c shunt shunt capacitance crystal @ 32.768 khz 0.6 2 pf 13.4.5 3 to 20 mhz crystal oscillator characteristics table 13 - 20. 3 to 20 mhz crystal oscillator characteristics symbol parameter conditions min typ max unit f req operating frequency normal mode with crystal 3 16 20 mhz supply ripple voltage (on vddpll) rms value, 10 khz to 10 mhz 30 mv duty cycle 40 50 60 % t on startup time 3 mhz, c shunt = 3pf 8 mhz, c shunt = 7pf 16 mhz, c shunt = 7pf with cm = 8ff 16 mhz, c shunt = 7pf with cm = 1.6ff 20 mhz, c shunt = 7pf 14.5 4 1.4 2.5 1 ms i dd_on current consumption (on vddio) 3 mhz ( 2 ) 8 mhz ( 3 ) 16 mhz ( 4 ) 20 mhz ( 5 ) 230 300 390 450 350 400 470 560 a p on drive level 3 mhz 8 mhz 16 mhz, 20 mhz 15 30 50 w r f internal resistor between xin and xout 0.5 m ? c lext maximum external capacitor on xin and xout 12.5 17.5 pf c l internal equivalent load capacitance integrated load capacitance (xin and xout in series) 7.5 9.5 10.5 pf www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 160 note: 1. r s = 100 - 200 ohms; cs = 2.0 - 2.5pf; cm = 2 ? 1.5 ff(typ, worst case) using 1 k a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 161 13.4.7 crystal oscillator design considerations information 13.4.7.1 choosing a crystal when choosing a crystal for the 32768 hz slow clock oscillator or for the 3 - 20 mhz oscillator, several parameters must be taken into account. important parameters between crystal and sam4s specifications are as follows: ? load capacitance ? c crystal is the equivalent capacitor value the oscillator must ?show? to the crystal in order to oscillate at the target frequency. the crystal must be chosen according to the internal load capacitance (c l ) of the on - chip oscillator. having a mismatch for the load capacitance will result in a frequency drift. ? drive level ? crystal drive level >= oscillator drive level. having a crystal drive level number lower than the oscillator specification may damage the crystal. ? equivalent series resistor (esr) ? crystal esr <= os cillator esr max. having a crystal with esr value higher than the oscillator may cause the oscillator to not start. ? shunt capacitance ? max. crystal shunt capacitance <= oscillator shunt capacitance ( c shunt ). having a crystal with esr value higher than the o scillator may cause the oscillator to not start. 13.4.7.2 printed circuit board (pcb) sam4sp32a oscillators are low power oscillators requiring particular attention when designing pcb systems. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 162 13.5 plla, pllb characteristics table 13 - 22. supply voltage phase lock loop characteri stics symbol parameter conditions min typ max unit vddpll supply voltage range 1.08 1.2 1.32 v allowable voltage ripple rms value 10 khz to 10 mhz rms value > 10 mhz 20 10 mv table 13 - 23. plla and pllb characteristics symbol parameter conditions min typ max unit f in input frequency 3 32 mhz f out output frequency 80 240 mhz i pll current consumption active mode @ 80 mhz @1.2v active mode @ 96 mhz @1.2v active mode @ 160 mhz @1.2v active mode @240 mhz @1.2v 0.94 1.2 2.1 3.34 1.2 1.5 2.5 4 ma t start settling time 60 150 s www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 163 13.6 usb transceiver characteristics 13.6.1 typical connections for typical connection please refer to the usb device section. 13.6.2 electrical characteristics table 13 - 24. electrical characteristics symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensitivity |(d+) - (d - )| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 9.18 pf i hi - z state data line leakage 0v < v in < 3.3v - 10 +10 a r ext recommended external usb series resistor in seri es with each usb pin with 5% 27 ? output levels v ol low level output measured with r l of 1.425 k ? tied to 3.6v 0.0 0.3 v v oh high level output measured with r l of 14.25 k ? tied to gnd 2.8 3.6 v v crs output signal crossover voltage measure conditions described in figure 13 - 9 1.3 2.0 v consumption i vddio current consumption transceiver enabled in input mode ddp = 1 and ddm = 0 105 200 a i vddcore current consumption 80 150 a www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 164 table 13 - 23. electrical characteristics (continued) symbol parameter conditions min typ max unit pull - up resistor r pui bus pull - up resistor on upstream port (idle bus) 0.900 1.575 k? r pua bus pull - up resistor on upstream port (upstream port receiving) 1.425 3.090 k? 13.6.3 switching characteristics table 13 - 24. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 % figure 13 - 9. u sb data signal rise and fall times www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 165 13.7 analog comparator characteristics table 13 - 25. analog comparator characteristics parameter conditions min typ max units voltage range the analog comparator is supplied by vddin 1.62 3.3 3.6 v input voltage range gnd + 0.2 vddin - 0.2 v input offset voltage 20 mv current consumption on vddin low power option (isel = 0) high speed option (isel = 1) 25 170 a hysteresis hyst = 0x01 or 0x10 hyst = 0x11 15 30 50 90 mv settling time given for overdrive > 100 mv low power option high speed option 1 0.1 s www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 166 13.8 temperature sensor the temperature sensor is connected to channel 15 of the adc. the temperature sensor provides an output voltage (v t ) that is proportional to absolute temperature (ptat). the v t output voltage linearly varies with a temperature slope dv t /dt = 4.72 mv/c. the v t voltage equals 1.44v at 27c, with a 50mv accuracy. the v t slope versus temperature dv t /dt = 4.72 mv/c only shows a 8% slight variation over process, mismatch and suppl y voltage. the user needs to calibrate it (offset calibration) at ambient temperature in order to get rid of the vt spread at ambient temperature (+/ - 15%). table 13 - 26. temperature sensor characteristics symbol parameter conditions min typ max units v t output voltage t = 27 c 1.44 v a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 167 13.9 ac characteristics 13.9.1 master clock characteristics table 13 - 27. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency vddcore @ 1.20v 120 mhz 1/(t cpmck ) master clock frequency vddcore @ 1.08v 100 mhz 13.9.2 i/o characteristics criteria used to define the maximum frequency of the i/os: ? output duty cycle (40% - 60%) ? minimum output swing: 100 mv to vddio - 100 mv ? minimum output swing: 100 mv to vddio - 100 mv ? addition of rising and falling time inferior to 75% of the period www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 16 8 table 13 - 28. i/o characteristics symbol parameter conditions min max units freqmax1 pin group 1 (1) maximum output frequency 10 pf v ddio = 1.62v 70 mhz 30 pf v ddio = 1.62v 45 pulseminh 1 pin group 1 (1) high level pulse width 10 pf v ddio = 1.62v 7.2 ns 30 pf v ddio = 1.62v 11 pulseminl 1 pin group 1 (1) low level pulse width 10 pf v ddio = 1.62v 7.2 ns 30 pf v ddio = 1.62v 11 freqmax2 pin group 2 ( 2 ) maximum output frequency 10 pf v ddio = 1.62v 46 mhz 25 pf v ddio = 1.62v 23 pulseminh 2 pin group 2 ( 2 ) high level pulse width 10 pf v ddio = 1.62v 11 ns 25pf v ddio = 1.62v 21.8 pulseminl 2 pin group 2 ( 2 ) low level pulse width 10 pf v ddio = 1.62v 11 ns 25 pf v ddio = 1.62v 21.8 freqmax3 pin group3 ( 3 ) maximum output frequency 10 pf v ddio = 1.62v 70 mhz 25 pf v ddio = 1.62v 35 pulseminh 3 pin group 3 ( 3 ) high level pulse width 10 pf v ddio = 1.62v 7.2 ns 25 pf v ddio = 1.62v 14.2 pulseminl 3 pin group 3 ( 3 ) low level pulse width 10 pf v ddio = 1.62v 7.2 ns 25 pf v ddio = 1.62v 14.2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 169 table 13 - 28. i/o characteristics symbol parameter conditions min max units freqmax4 pin group 4 (4) maximum output frequency 10 pf v ddio = 1.62v 58 mhz 25 pf v ddio = 1.62v 29 pulseminh 4 pin group 4 (4) high level pulse width 10 pf v ddio = 1.62v 8.6 ns 25pf v ddio = 1.62v 17.2 pulseminl 4 pin group 4 (4) low level pulse width 10 pf v ddio = 1.62v 8.6 ns 25 pf v ddio = 1.62v 17.2 freqmax5 pin group 5 (5) maximum output frequency 25 pf v ddio = 1.62v 25 mhz note: 1. pin group 1 = pa14, pa29 2. pin group 2 = pa[4 - 11], pa[15 - 25], pa[30 - 31], pb[0 - 9], pb[12 - 14], pc[0 - 31] 3. pin group 3 = pa[12 - 13], pa[26 - 28], pa[30 - 31] 4. pin group 4 = pa[0 - 3] 5. pin group 5 = pb[10 - 11] 13.9.3 ssc timings timings are given in the following domain: 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 20 pf 3.3v domain: vddio from 2.85v to 3.6v, maximum external capacitor = 30 pf . figure 13 - 10. ssc transmitter, tk and tf as output tk ( cki =1) tf/td ssc 0 tk ( cki =0) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 170 figure 13 - 11. ssc transmitter, tk as input and tf as output figure 13 - 12. ssc transmitter, tk as output and tf as input figure 13 - 13. ssc transmitter, tk and tf as input tk ( cki =1) tf/td ssc 1 tk ( cki =0) tk ( cki=1) tf ssc 2 ssc 3 tk ( cki=0) td ssc 4 tk ( cki=0) tf ssc 5 ssc 6 tk ( cki=1) td ssc 7 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 171 figure 13 - 14. ssc receiver rk and rf as input figure 13 - 15. ssc receiver, rk as input and rf as output figure 13 - 16. ssc receiver, rk and rf as output rk ( cki=1) rf/rd ssc 8 ssc 9 rk ( cki=0) rk ( cki=0) rd ssc 8 ssc 9 rk ( cki=1) rf ssc 10 rk ( cki=0) rd ssc 11 ssc 12 rk ( cki=1) rf ssc 13 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 172 figure 13 - 17. ssc receiver, rk as output and rf as input rk ( cki=1) rf/rd ssc 11 ssc 12 rk ( cki=0) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 173 13.9.3.2 ssc timings table 13 - 29. ssc timings symbol parameter condition min max units transmitter ssc 0 tk edge to tf/td (tk output, tf output) 1.8v domain (3) 3.3v domain ( 4 ) - 3 - 2.6 5.4 5.0 ns ssc 1 tk edge to tf/td (tk input, tf output) 1.8v domain (3) 3.3v domain ( 4 ) 4.5 3.8 16.3 13.3 ns ssc 2 tf setup time before tk edge (tk output) 1.8v domain (3) 3.3v domain ( 4 ) 14.8 12.0 ns ssc 3 tf hold time after tk edge (tk output) 1.8v domain (3) 3.3v domain ( 4 ) 0 ns ssc 4 ( 1 ) tk edge to tf/td (tk output, tf input) 1.8v domain (3) 3.3v domain ( 4 ) 2.6(+2*t cpmck ) ( 1 ) (4) 2.3(+2*t cpmck ) ( 1 ) (4) 5.4(+2*t cpmck ) ( 1 ) (4) 5.0(+2*t cpmck ) ( 1 ) (4) ns ssc 5 tf setup time before tk edge (tk input) 1.8v domain (3) 3.3v domain ( 4 ) 0 ns ssc 6 tf hold time after tk edge (tk input) 1.8v domain (3) 3.3v domain ( 4 ) t cpmck ns ssc 7 ( 1 ) tk edge to tf/td (tk input, tf input) 1.8v domain (3) 3.3v domain ( 4 ) 4.5(+3*t cpmck ) ( 1 ) (4) 3.8(+3*t cpmck ) ( 1 ) (4) 16.3(+3*t cpmck ) ( 1 ) (4) 13.3(+3*t cpmck ) ( 1 ) (4) ns receiver ssc 8 rf/rd setup time before rk edge (rk input) 1.8v domain (3) 3.3v domain ( 4 ) 0 ns ssc 9 rf/rd hold time after rk edge (rk input) 1.8v domain (3) 3.3v domain ( 4 ) t cpmck ns ssc 10 rk edge to rf (rk input) 1.8v domain (3) 3.3v domain ( 4 ) 4.7 4 16.1 12.8 ns ssc 11 rf/rd setup time before rk edge (rk output) 1.8v domain (3) 3.3v domain ( 4 ) 15.8 - t cpmck 12.5 - t cpmck ns ssc 12 rf/rd hold time after rk edge (rk output) 1.8v domain (3) 3.3v domain ( 4 ) t cpmck - 4.3 t cpmck - 3.6 ns ssc 13 rk edge to rf (rk output) 1.8v domain (3) 3.3v domain ( 4 ) - 3 - 2.6 4.3 3.8 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 174 note: 1. timings ssc4 and ssc7 depend on the start condition. when sttdly = 0 (receive start delay) and start = 4, or 5 or 7(receive start selection), two periods of the mck must be added to timings. 2. for output signals (tf, td, rf), min and max access times are defined. the min access time is the time between the tk (or rk) edge and the signal change. the max access timing is the time between the tk edge and the signal stabilization. figure 13 - 18 illustrates min and max accesses for ssc0. the same applies for ssc1, ssc4, and ssc7, ssc10 and ssc13. 3. 1.8v domain: v vddio from 1.65v to 1.95v, maximum external capacitor = 20 pf. 4. 3.3v domain: v vddio from 2.85v to 3.6v, maximum external capacitor = 30 pf.. figure 13 - 18. min and max access time of output signals tk ( cki =0) tf/td ssc 0min tk ( cki =1) ssc 0max www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 175 13.9.4 smc timings timings are given in the following domain: 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 30 pf 3.3v domain: vddio from 2.85v to 3.6v, maximum external capacitor = 50 pf . timings are given assuming a capacitance load on data, control and address pads: in the following tables t cpmck is mck period. timing extraction 13.9.4.1 read timings table 13 - 30. smc read signals - nrd controlled (read_mode = 1) symbol parameter min max units vddio supply 1.8 v (2) 3.3v ( 3 ) 1.8v (2) 3.3v ( 3 ) no hold settings (nrd hold = 0) smc 1 data setup before nrd high 19.9 17.9 ns smc 2 data hold after nrd high 0 0 ns hold settings (nrd hold a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 176 table 13 - 31. smc read signals - ncs controlled (read_mode= 0) symbol parameter min max units vddio supply 1.8v (2) 3.3v ( 3 ) 1.8v (2) 3.3v ( 3 ) no hold settings (ncs rd hold = 0) smc 8 data setup before ncs high 20.7 18.4 ns smc 9 data hold after ncs high 0 0 ns hold settings (ncs rd hold a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 177 13.9.4.2 write timings table 13 - 32. smc write signals - nwe controlled (write_mode = 1) symbol parameter min max units 1.8v (2) 3.3v ( 3 ) 1.8v (2) 3.3v ( 3 ) hold or no hold settings (nwe hold < symbol>1 0, nwe hold = 0) smc 15 data out valid before nwe high nwe pulse * t cpmck - 6.9 nwe pulse * t cpmck - 6.7 ns smc 16 nwe pulse width nwe pulse * t cpmck - 7.3 nwe pulse * t cpmck - 6.3 ns smc 17 a0 - a22 valid before nwe low nwe setup * t cpmck - 7.2 nwe setup * t cpmck - 7.0 ns smc 18 ncs low before nwe high (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 7.1 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 6.8 ns hold settings (nwe hold a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 178 table 13 - 33. smc write ncs controlled (write_mode = 0) symbol parameter min max units 1.8v (2) 3.3v ( 3 ) 1.8v (2) 3.3v ( 3 ) smc 22 data out valid before ncs high ncs wr pulse * t cpmck - 6.3 ncs wr pulse * t cpmck - 6.2 ns smc 23 ncs pulse width ncs wr pulse * t cpmck - 7.7 ncs wr pulse * t cpmck - 6.7 ns smc 24 a0 - a22 valid before ncs low ncs wr setup * t cpmck - 6.5 ncs wr setup * t cpmck - 6.3 ns smc 25 nwe low before ncs high ( ncs wr setup - nwe setup + ncs pulse)* t cpmck - 5.1 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 4.9 ns smc 26 ncs high to data out,a0 - a25, change ncs wr hold * t cpmck - 10.2 ncs wr hold * t cpmck - 8.4 ns smc 27 ncs high to nwe inactive (ncs wr hold - nwe hold)* t cpmck - 7.4 (ncs wr hold - nwe hold)* t cpmck - 7.1 ns note: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs wr hold length? or ?nwe hold length?. 2. 1.8v domain: vddio from 1.65 v to 1.95v, maximum external capacitor = 30pf 3. 3.3v domain: vddio from2.85v to 3.6v, maximum external capacitor = 50pf. figure 13 - 19. smc timings - ncs controlled read and write nrd ncs data nwe ncs controlled read with no hold ncs controlled read with hold ncs controlled write smc22 smc26 smc10 smc11 smc12 smc9 smc8 smc14 smc14 smc23 smc27 smc26 a0 - a23 smc24 smc25 smc12 smc13 smc13 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 179 figure 13 - 20. smc timings - nrd controlled read and nwe controlled write nrd ncs data nwe a0-a23 nrd controlled read with no hold nwe controlled write with no hold nrd controlled read with hold nwe controlled write with hold smc1 smc2 smc15 smc21 smc3 smc4 smc15 smc19 smc20 smc7 smc21 smc16 smc7 smc16 smc19 smc21 smc17 smc18 smc5 smc5 smc6 smc6 smc17 smc18 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 180 13.9.5 usart in spi mode timings timings are given in the following domain: 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 20 pf 3.3v domain: vddio from 2.85v to 3.6v, maximum external capacitor = 40 pf . figure 13 - 21. usart spi master mode figure 13 - 22. usart spi slave mode: (mode 1 or 2) nss spi 0 msb lsb spi 1 cpol=1 cpol=0 miso mosi sck spi 5 spi 2 spi 3 spi 4 spi 4 ? the mosi line is d r i v en b y the output pin t xd ? the miso line d r i v es the input pin r xd ? the sck line is d r i v en b y the output pin sck ? the nss line is d r i v en b y the output pin r t s sck miso mosi spi 6 spi 7 spi 8 nss spi 12 spi 13 ? the mosi line d r i v es the input pin r xd ? the miso line is d r i v en b y the output pin t xd ? the sck line d r i v es the input pin sck ? the nss line d r i v es the input pin c t s www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 181 figure 13 - 23. usart spi sla ve mode: (mode 0 or 3) sck miso mosi spi 9 spi 10 spi 11 nss spi 14 spi 15 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 182 13.9.5.2 usart spi timings table 13 - 34. usart spi timings symbol parameter conditions min max units master mode spi 0 sck period 1.8v domain 3.3v domain mck/6 ns spi 1 input data setup time 1.8v domain 3.3v domain 0.5 * mck + 0.8 0.5 * mck + 1.0 ns spi 2 input data hold time 1.8v domain 3.3v domain 1.5 * mck + 0.3 1.5 * mck + 0.1 ns spi 3 chip select active to serial clock 1.8v domain 3.3v domain 1.5 * spck - 1.5 1.5 * spck - 2.1 ns spi 4 output data setup time 1.8v domain 3.3v domain - 7.9 - 7.2 9.9 10.7 ns spi 5 serial clock to chip select inactive 1.8v domain 3.3v domain 1 * spck - 4.1 1 * spck - 4.8 ns slave mode spi 6 sck falling to miso 1.8v domain 3.3v domain 4.7 4 17.3 15.2 ns spi 7 mosi setup time before sck rises 1.8v domain 3.3v domain 2 * mck + 0.7 2 * mck ns spi 8 mosi hold time after sck rises 1.8v domain 3.3v domain 0 0.1 ns spi 9 sck rising to miso 1.8v domain 3.3v domain 4.7 4.1 17.1 15.5 ns spi 10 mosi setup time before sck falls 1.8v domain 3.3v domain 2 * mck + 0.7 2 * mck + 0.6 ns spi 11 mosi hold time after sck falls 1.8v domain 3.3v domain 0.2 0.1 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 183 table 13 - 34. usart spi timings (continued) symbol parameter conditions min max units spi 12 npcs0 setup to sck rising 1.8v domain 3.3v domain 2,5 * mck + 0.5 2,5 * mck ns spi 13 npcs0 hold after sck falling 1.8v domain 3.3v domain 1,5 * mck + 0.2 1,5 * mck ns spi 14 npcs0 setup to sck falling 1.8v domain 3.3v domain 2,5 * mck + 0.5 2,5 * mck + 0.3 ns spi 15 npcs0 hold after sck rising 1.8v domain 3.3v domain 1,5 * mck 1,5 * mck ns note: 1. 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 20 pf 2. 3.3v domain: vddio from2.85v to 3.6v, maximum external capacitor = 40 pf. www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 184 13.9.6 two - wire serial interface characteristics following table describes the requirements for devices connected to the two - wire serial bus. for timing symbols refer to figure 13 - 24 table 13 - 35. two - wire serial bus requirements symbol parameter condition min max units v il input low - voltage - 0.3 0.3 v vddio v v ih input high - voltage 0.7xv vddio v cc + 0.3 v v hys hyst eresis of schmitt trigger inputs 0.150 ? v v ol output low - voltage 3 ma sink current - 0.4 v t r rise time for both twd and twck 20 + 0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf figure 13 - 24 20 + 0.1c b (1)(2) 250 ns c i (1) capacitance for each i/o pin ? 10 pf f tw ck twck clock frequency 0 400 khz rp value of pull - up resistor f tw ck 100 khz ? f tw ck > 100 khz ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 185 table 13 - 35. two - wire serial bus requirements (continued) symbol parameter condition min max units t low low period of the twck clock f tw ck 100 khz (3) ? s f tw ck > 100 khz (3) ? s t high high period of the twck clock f tw ck 100 khz (4) ? s f tw ck > 100 khz (4) ? s t hd;sta hold time (repeated) start condition f tw ck 100 khz t high ? s f tw ck > 100 khz t high ? s t su;sta set - up time for a repeated start condition f tw ck 100 khz t high ? s f tw ck > 100 khz t high ? s t hd;dat data hold time f tw ck 100 khz 0 3 x t cp_mck (5) s f tw ck > 100 khz 0 3 x t cp_mck (5) s t su;dat data setup time f tw ck 100 khz t low - 3 x t cp_mck (5) ? ns f tw ck > 100 khz t low - 3 x t cp_mck (5) ? ns t su;sto setup time for stop condition f tw ck 100 khz t high ? s f tw ck > 100 khz t high ? s t hd;sta hold time (repeated) start condition f tw ck 100 khz t high ? s f tw ck > 100 khz t high ? s note: 1. required only for f tw ck > 100 khz. 2. c b = capacitance of one bus line in pf. per i2c standard, c b max = 400pf 3. the twck low period is defined as follows:t low = ((cldiv x 2 ckdiv ) + 4) x t mck 4. the twck high period is defined as follows: t high = ((chdiv x 2 ckdiv ) + 4) x t mck 5. t cp_mck = mck bus period. figure 13 - 24. two - wire serial bus timing t su;st a t l o w t high t l o w t of t hd;st a t hd;d a t t su;d a t t su;st o t b uf t wck t wd t r www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 186 13.9.7 embedded flash characteristics the maximum operating frequency is given in table 13 - 36 to table 13 - 39 below but is limited by the embedded flash access time when the processor is fetching code out of it. the tables below give the device maximum operating frequency depending on the field fws of the mc_fmr register. this field de fines the number of wait states required to access the embedded flash memory. the embedded flash is fully tested during production test, the flash contents are not set to a known state prior to shipment. therefore, the flash contents should be erased prio r to programming an application. table 13 - 36. embedded flash wait state vddcore set at 1.08v and vddio 1.62v to 3.6v @85c fws read operations maximum operating frequency (mhz) 0 1 cycle 16 1 2 cycles 33 2 3 cycles 50 3 4 cycles 67 4 5 cycles 84 5 6 cycles 100 table 13 - 37. embedded flash wait state vddcore set at 1.08v and vddio 2.7v to 3.6v @85c fws read operations maximum operating frequency (mhz) 0 1 cycle 20 1 2 cycles 40 2 3 cycles 60 3 4 cycles 80 4 5 cycles 100 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 187 table 13 - 38. embedded flash wait state vddcore set at 1.2v and vddio 1.62v to 3.6v @ 85c fws read operations maximum operating frequency (mhz) 0 1 cycle 17 1 2 cycles 34 2 3 cycles 52 3 4 cycles 69 4 5 cycles 87 5 6 cycles 104 6 7 cycles 121 table 13 - 39. embedded flash wait state vddcore set at 1.20v and vddio 2.7v to 3.6v @ 85c fws read operations maximum operating frequency (mhz) 0 1 cycle 21 1 2 cycles 42 2 3 cycles 63 3 4 cycles 84 4 5 cycles 105 5 6 cycles 123 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 188 table 13 - 40. ac flash characteristics parameter conditions min typ max units program cycle time erase page mode 10 50 ms erase block mode (by 4kbytes) 50 200 ms erase sector mode 400 950 ms full chip erase 1 mbytes 512 kbytes 9 5.5 18 11 s data retention not powered or powered 20 years endurance write/erase cycles per page, block or sector @ 25c write/erase cycles per page, block or sector @ 85c 10k 100k cycles www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 189 13.10 recommended operating conditions table 13 - 41. sam4sp32a recommended operating conditions parameter symbol rating unit min typ max supply voltage v v ddcore 1.08 1.20 1.32 v v v ddin 3.00 3.30 3.60 v vd dio 3.00 3.30 3.60 v v ddpll 1.08 -- 1.32 a vdd 3.00 3.30 3.60 junction temperature tj - 40 25 + 125 oc ambient temperature ta - 40 -- + 85 www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 190 14. mechanical characteristics figure 14 - 1. 128- lead lqfp package mechanical drawing www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 191 15. ordering information table 15 - 1. atmel sam4sp32a ordering codes atmel ordering code package package type temperature range at sam4sp32a - a n u - y 128 lqfp pb - free industrial ( - 40oc to 85o) atsam4 sp32a - anu- yxx atmel designator product family device designator device revision customer marking shipping carrier option package device grade or wafer/die thickness package option u = lead free (pb-free) industrial temperature range (-40c to +85c) y = tray an = 128lqfp at=atmel p=power line communications a=prime 1.3.6 compliant flash size 32=2mbytes (2x1024kb, dual bank) www.datasheet.net/ datasheet pdf - http://www..co.kr/ a tmel sam4sp32a [ prelim in ary datasheet ] 43020a - atpl - 09/12 192 16. revision history doc. rev. date comments a 10 /2012 initial release www.datasheet.net/ datasheet pdf - http://www..co.kr/ atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1)(408) 441 - 0311 fax: (+1)(408) 487 - 2600 www.atmel.com atmel asia limited unit 01 - 5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245 - 6100 fax: (+852) 2722 - 1369 atmel munich gmbh business campus parkring 4 d - 85748 garching b. munich germany tel: (+49) 89 - 31970 - 0 fax: (+49) 89 - 3194621 atmel japan g.k. 16f shin - osaki kangyo building 1 - 6 - 4 osaki shinagawa - ku, tokyo 141 - 0032 japan tel: (+81)(3) 6417 - 0300 fax: (+81)(3) 6417 - 03 70 ? 201 2 atmel corporation. all rights reserved. / rev.: 43020a - atpl - 09/12 atmel?, logo and combinations thereof, sam - ba? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. arm?, arm?powered logo, cortex?, thumb? - 2 and others are registered trademarks or trademarks of arm ltd.other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, b y estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel pro ducts. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the i mplied warranty of merchantability, fitness for a particular purpose , or non - infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitation, damages for loss a nd profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of s uch damages. atmel makes no representations or warranties with respect to the accurac y or completeness of the contents of this document and reserves the right to make changes to specifications and products desc riptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specific ally provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications inte nded to support or sustain life. www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
Price & Availability of ATSAM4SP32A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |